03-27-2017 06:45 PM
Requirements: My design uses 4 RX and 4 TX channels from 1 GTY quad at a combined bandwidth of 10 Gbps. I require the use of a shared clock between all channels to negate phase differences between channels; therefore, I am attempting to implement TX and RX Buffer Bypass in Multi-Lane Auto Mode (p. 149 in ug578).
Problem: As illustrated in Figure 3-25 (ug578), master and slave channels require specific inputs and wiring. While the GTYE4 channel primitives are the same, each primitive instantiation requires different values for their inputs. The wizard does not seem to allow individual access to the inputs and outputs to EACH GTY channel WITHIN one quad. I require this access to be able to configure the channels for this clock sharing between channels.
Additionally, some GTY ports do not seem to be available with the Wizard, such as RXSYNC_SKIP_DA, which I require access to.
03-28-2017 06:09 AM
04-11-2017 05:18 PM
I can confirm that enabling RX and TX Buffer Bypass causes the GT wizard to disable/enable visibility of CERTAIN ports, but not ALL important ports to fully configure Multi-Lane Auto Mode.
Moreover, there is no visibility of ports for EACH INDIVIDUAL GT channel. I require access to these to properly configure each channels' transceiver settings.
1) Because the wizard doesn't seem to allow access to individual channels' ports, I could instantiate the GT quad/channel primitives and perform the necessary port configuration myself (I can see the missing ports in the write-protected GT primitive files), although going this route would require extensive coding.
04-12-2017 04:47 AM
04-17-2018 09:51 AM
To enable the settings discussed here for "TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode" in UG576, that RXSYNC_SKIP_DA setting for only the master RX channel (not all channels) should be set to 1'b1. However, nothing in the Transceiver Wizard indicates how to expose this parameter (NOT a port) for following these guidelines.
As of version 1.7 of the Ultrascale FPGAs Transceivers Wizard, the required parameter of RXSYNC_SKIP_DA is hard-coded to a value of 1'b0 deep in the hierarchy of generated RTL when both TX and RX buffers are set to Bypass mode. The file "<IP component name>_gthe4_channel_wrapper.v" is labeled "DO NOT MODIFY THIS FILE" - the same for several files above that in the hierarchy. That is the file in which RXSYNC_SKIP_DA is hard-coded to 1'b0.
What is the recommended method for accessing the RXSYNC_SKIP_DA parameter? If it is meant to be exposed when Bypass mode is enabled for both RX and TX buffers, when can we expect a fix and what can we do to change this setting until the fix is available (XDC or synthesis directive, etc.)?
Kind Regards, Matt Keener
04-18-2018 12:04 AM
AR 70869 - TX Lane to Lane Alignment describes how to deskew lanes with sub UI precision, without getting rid of the TXBUFFER.
It will be public soon.