05-16-2018 04:14 AM
Generated the GTY Transceiver Example design. Tried to simulate the example design(PMA Loopback) in vivado
simulator vivado 2018.1. i can see the mismatch in the received rx data with tx data. i have attached the
screenshot of GTY Preset and simulation waveform. please help me to resolve the issue.
TX Data = 32'ha7ed0409
RX Data = 32'h4fda0813
Here received rx data is shifted data of tx data. For reference, marked in the screenshot.
Device : Xilinx XCVU9P-2FSGD2104E Virtex UltraScale +
Tool : Vivado 2018.1
05-16-2018 05:32 AM
the data shift is expected. You have some latency in the transceiver that you cannot avoid.
05-22-2018 08:12 AM - edited 05-22-2018 08:21 AM
For instance, the data coming into the TX portion of the has to be registered into the internal registers in the TX interface. That takes one clock cycle then if you use 8B10B encoding that takes another full clock cycle. Coming out of the RX portion you would have similar registers to unencode and send the data to the interface. That would delay the input to the output 4 usrclk cycles right there. The delay is referred to as latency and there is a table where the full input and output delay/latency for a particular setup can be calculated here: http://www.xilinx.com/support/answers/66341.htm
In addition to the full clock cycles in the analog section there are partial clock cycles in that latency. If you want the data to be realigned so that A7 reads as A7 you would need to use an encoding scheme such as 64/66 or 8B10B so that the input data can be realigned by the receiver. For an 8B10B encoding you would also have to enable comma alignment in the wizard. See the Byte alignment section of the User Guide.