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miguel.jimenez
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Registered: ‎05-09-2018

GTY Ultrascale+ Phase Interpolator frequency limitation

Hello Xilinx experts,

I would like to ask for a specific doubt regarding the Phase Interpolator module inside the GTY transceiver for the Ultrascale+ devices. UG578 [1] presents the GTY transceivers for the Ultrascale devices, albeit I did not find any document for the Ultrascale+ family. Consequently, I have reviewed the Phase Interpolator section (page 164) and I found the following:

"The interconnect logic can control the TX PI in the TX PMA through the use of the TX phase interpolator PPM controller module in the PCS. The TX phase interpolator PPM controller module is only supported for line rates up to 16.375 Gb/s."

However, I am not sure if this frequency limitation for the Phase Interpolator block is also presented for the GTY transceivers of the Ultrascale+ devices. 

Could you clarify this point?

Thanks in advance,

Best Regards.

Miguel J.

[1]: https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf

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roym
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Registered: ‎07-30-2007

UG578 covers both US and US+.  Where there are difference between the 2 it is pointed out in the text.  See TXPI_PPM definition at the bottom of page 165. (v1.3) for an example of this.  




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miguel.jimenez
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Registered: ‎05-09-2018

Hello again,

Thanks for your quick response. However, it is not so clear for me. If you check [1] in page 2 (the footnote concretelly), it says:

"The maximum supported line rate with the fPLL is 16.4 Gb/s for GTY transceivers in UltraScale FPGAs and GTH transceivers in Ultrascale+ FPGAs."

So, my question is: Is this limitation also applicable to GTY in the Ultrascale+ family devices? I mean, here, GTH in this family is clear but not for GTY.

Could you clarify this point?

Thanks in advance,

Best regards,

Miguel J.

[1]: https://www.xilinx.com/support/documentation/application_notes/xapp1276-vcxo.pdf

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roym
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Registered: ‎07-30-2007

The phase interpolator is different from the fractional PLL divider.  On page 48 it says that the fractional divider works at up to 28.1 Gbps.  I've asked one of the authors to weigh in on the limitations of that app note.




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miguel.jimenez
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Registered: ‎05-09-2018

Hello Roy,

You're right I did not realize that this sentence speaks about fPLL and not PI. Did you get additional information about note's authors?

On the other hand, my initial doubt is due to I would like to know if GTY primitive is able to work with the PI for 25Gbps rate. As we discussed previously, it is not possible using GTY (Ultrascale and Ultrascale+) because the UG578 is for both families. Is that correct? I found a reference [1] that confirm this for Ultrascale devices but no for Ultrascale+ ones.

If GTY can not be used, Is there any transceiver primitive whose PI could operate with 25Gbps rate?

Thanks a lot,

Best regards,

Miguel J.

[1]: https://www.xilinx.com/support/answers/62261.html

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borisq
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @miguel.jimenez 

 

I'm afraid 16.375Gbps is the upper limit for both US GTY and US+ GTY TX PI feature.

Are you using TX PI to track the recover clock frequency?

If so, you can use fractional PLL feature, instead of TX PI. Fractional PLL can support upto 28Gbps.

 

Thanks,

Boris

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