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Visitor
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Registered: ‎10-01-2019

GTY integrated and simulation

Hi All,

 

I get an error where BUF_GT is unresolved during the simulation. I am using the GTY files generated out of Vivado and integrated it with my own upper layers and trying to simulate it. Can you please let me know how I can resolve this and where do I get these files from?

Basically I would like to know where I would get the models for library cells of Xilinx to run the simulation.

Where can I find the library files used by Xilinx for GTY  and how do I use it?

I am using / running standalone Xcelium simulator from Cadence and is not under the hood of Vivado Environment.

 

Regards

Hariharan K Srinivasan.

 

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Visitor
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Registered: ‎10-01-2019

Re: GTY integrated and simulation

Hi All,

I have gotten some lead where I get to resolve the BUFG_GT and GTYE4_CHANNEL unresolved error. However I see that GTYE4_CHANNEL instantiates a protect module called SIP_GTYE4_CHANNEL. Any pointers as how I solve this?

Attached is the snapshot of error during elaboration in Xcelium simulator.

Regards

Hariharan K Srinivasan.

Sim_errorWithXcelium.png
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