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adun4
Observer
Observer
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Registered: ‎09-18-2012

GTY phase alignment & delay alignment in buffer bypass mode

There are two different concepts in TX/RX Buffer Bypass "phase alignment" and "delay alignment". But difference between them is obscure from documentation.

1) There is "Delay Aligner" block on Figure 3-30, but there is no block preforming phase alignment at any picture in documentation.

2) "Delay Aligner" is continuously adjusting the TXUSRCLK (actually master's TXOUTCLK). What signal is "phase alignment" changing?

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

hi @adun4,

 

phase and delay alignment are two different things but they work together in buffer bypass. For a description please have a look at the buffer bypass chapters for RX and TX in ug578.

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adun4
Observer
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Registered: ‎09-18-2012

Hi @eschidl,

I've read these chapters several times, but can't find answer to my questions.

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borisq
Xilinx Employee
Xilinx Employee
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Registered: ‎08-07-2007

hi @adun4

 

below is the difference between the two.

 

1, phase alignment happens immediately after resetdone asserting. it happens once after each reset. after phase alignment is done, it will not happen again until another reset is attempted.

 

delay alignment is continousely working to solve voltage and temperature variation during transceiver is operating.

 

2, during phasealignment,  TX or RX XCLK phase is adjusted to match TXUSRCLK or RXUSRCLK phase. when they are matched, then phase alignment is done.

during delay alignment, TXUSRCLK/RXUSRCLK phase is adjusted to overcome the phase offset caused by voltage and temperature variation, so that TXUSRCLK/RXUSRCLK phase can be still.

 

Thanks,

Boris

 

 

 

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adun4
Observer
Observer
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Registered: ‎09-18-2012

@borisqThanks for your answer! But I have more questions:


1) Delay alignment is done by adjusting master RXOUTCLK/TXOUTCLK (source of RXUSRCLK/TXUSRCLK in multilane application)?
2) Is Phase Interpolator in charge of phase alignment?
3) How initialization sequence master_phase -> master_delay -> slave_phase -> master_delay should be changed in case "TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode" ? I have problems with reliable communication in such configuration and without deep understanding of underlaying process it's difficult to debug system.

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borisq
Xilinx Employee
Xilinx Employee
1,395 Views
Registered: ‎08-07-2007

hi @adun4

 

1) Delay alignment is done by adjusting master RXOUTCLK/TXOUTCLK (source of RXUSRCLK/TXUSRCLK in multilane application)?

 

yes.


2) Is Phase Interpolator in charge of phase alignment?

i think yes.


3) How initialization sequence master_phase -> master_delay -> slave_phase -> master_delay should be changed in case "TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode" ? I have problems with reliable communication in such configuration and without deep understanding of underlaying process it's difficult to debug system.

you don't need to change that. you can use the example code in our example design.

what problem did you see? 

please provide more details:

a, line rate

b, TX or RX

c, any ILA waveforms?

 

Thanks,

Boris

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