UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Contributor
Contributor
314 Views
Registered: ‎03-04-2016

GTY simulation with reset FSM: GTPOWERGOOD always zero

Hi,

currently I try to simulate my generated GTY transceiver.

In the documentation the following picture is provided:

GTY_doc.PNG

At first I do the GTTXRESET (using the 'gtwiz_reset_tx_pll_and_datapath_in') port.

After that I can see the TX RESET FSM is in state 'ST_RESET_ALL_TX_PLL_WAIT' ('sm_reset_all[2:0] = '011').

The QPLL0RESET is '1', too, after the 'ST_RESET_ALL_TX_PLL' state.

Now I would expect the GTPOWERGOOD goes high (over 50 ms simulation time) but it does not!

Obviously my PLL won't lock, because GTPOWERGOOD has to be high.

 

Here a snapshot of the TX RESET FSM in my simulation (time unit is in us; freerunning clock = 15 MHz):

Sim_TX_reset.PNG

 

Furthermore I've tried to reset the GTY using the 'gtwiz_reset_all_in' but without success. Again I'm stucking in state 'ST_RESET_ALL_TX_PLL_WAIT' with GTPOWERGOOD = 0 (over 50 ms simulation time).

 

Is there a further signal I have to drive for a GTPOWERGOOD indication?

Which issue in my reset control of the GT_WIZ - reset ports could cause this strange behaviour?

 

I'm using the Vivado 2018.3 version. Simulating with VCS-N-2017.12-SP2-4 (Full64) at Linux SuSe.

I've created all simulation libraries in Vivado for this specific VCS version

Best regards,

  Michael

0 Kudos
1 Reply
Moderator
Moderator
288 Views
Registered: ‎07-30-2007

Re: GTY simulation with reset FSM: GTPOWERGOOD always zero

Is it possible you are missing a reference clock to the GT or the freerunning clock input to the design?  This is unusual in that you should be creating an example design that will deliver a working example design simulation.  If you have done this simulation on your own you should be able to compare to the example design simulation.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------


0 Kudos