cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
upside_down
Visitor
Visitor
615 Views
Registered: ‎11-06-2019

GTY transceiver TX buffer and TX phase allignment

Jump to solution

I am reading the user guide of GTY transceivers (ug578). In page 138 it talks about TX buffer bypassing, and there is corresponding figure which should show the corresponding datapath (Figure 3-18, screenshot is attached below). 

I am not sure which block is TX buffer and which one is TX phase alignment block (I have a guess but I want to be sure). I need to know the exact blocks to understand the dataflow path when TX buffer is bypassed. 

Which part/block is TX buffer and which one is TX phase alignment?

Screenshot_20191205-111453.png
0 Kudos
Reply
1 Solution

Accepted Solutions
eschidl
Xilinx Employee
Xilinx Employee
585 Views
Registered: ‎10-19-2011

Hi @upside_down ,

the TX buffer is the phase adjust FIFO in the diagram. The phase alignment circuit for buffer bypass is not explicitely drawn in that diagram.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post

1 Reply
eschidl
Xilinx Employee
Xilinx Employee
586 Views
Registered: ‎10-19-2011

Hi @upside_down ,

the TX buffer is the phase adjust FIFO in the diagram. The phase alignment circuit for buffer bypass is not explicitely drawn in that diagram.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------

View solution in original post