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Visitor upside_down
Visitor
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Registered: ‎11-06-2019

GTY transceiver TX buffer and TX phase allignment

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I am reading the user guide of GTY transceivers (ug578). In page 138 it talks about TX buffer bypassing, and there is corresponding figure which should show the corresponding datapath (Figure 3-18, screenshot is attached below). 

I am not sure which block is TX buffer and which one is TX phase alignment block (I have a guess but I want to be sure). I need to know the exact blocks to understand the dataflow path when TX buffer is bypassed. 

Which part/block is TX buffer and which one is TX phase alignment?

Screenshot_20191205-111453.png
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Xilinx Employee
Xilinx Employee
253 Views
Registered: ‎10-19-2011

Re: GTY transceiver TX buffer and TX phase allignment

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Hi @upside_down ,

the TX buffer is the phase adjust FIFO in the diagram. The phase alignment circuit for buffer bypass is not explicitely drawn in that diagram.

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Xilinx Employee
Xilinx Employee
254 Views
Registered: ‎10-19-2011

Re: GTY transceiver TX buffer and TX phase allignment

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Hi @upside_down ,

the TX buffer is the phase adjust FIFO in the diagram. The phase alignment circuit for buffer bypass is not explicitely drawn in that diagram.

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View solution in original post