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k.rymarz
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Registered: ‎05-11-2018

GTY using recovered clock to feed transmitter

Hi

My design is latency critical, I am using GTY transceivers (UltraScale+) to receive and transmit data. I have my own PCS layer implemented in FPGA fabric, transceivers are configured to have lowest possible latency ( no comma alignment, elastic buffers, fifos etc.). Let's assume that I am receiving data from one GTY quad and transmitting data through another GTY quad.  Is it possible to use receiver clock recovered from data as a reference for quad used as transmitter ? My goal is to have 100% synchronous design without any CDC on path from RX to TX but without adding any additional latency. 

As far as I know I can bring RXOUTCLK outside FPGA, clean it through some PLL and then use it as a reference for transmitter quad but in this case RXOUTCLK and TXOUTCLK inside FPGA will still be asynchronous.

Would it be possible if I used same quad for RX and TX ?

Thanks for any help.

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roym
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Registered: ‎07-30-2007

I think what you are looking for is XAPP 1276.  This AR has information on other XAPPs that might help:  https://www.xilinx.com/support/answers/68928.html 

'1276 should allow you sync TX channels to a recovered clock (or any clock in the right frequency range).  https://www.xilinx.com/support/documentation/application_notes/xapp1276-vcxo.pdf

 




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k.rymarz
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Registered: ‎05-11-2018

Ok so it looks like I have 2 options:

Option 1. Take recovered clock outside FPGA, clean it and then use it as a reference clock for quad with transmitter. I have one question regarding this option. Will I be able to connect it like this: RXOUTCLK(quad A) -> BUFG GT -> TXUSERCLK (quad B) ? I assume that PMA Phase Alignment will be able to match phase between this new TXUSERCLK and serial clock from reference (recovered clock) as both have the same source. In this option everything is clear from STA perspective as I use single clock in FPGA fabric and only Phase Alignment is responsible for phase matching in the TX PMA layer. Am I correct?

Option 2. XAPP 1276. If I understand it correctly QPLL output frequency can be controlled through SDM and thanks to this we can synchronize TXOUTCLK with any clock (in my example it will be recovered clock). How it will look like in STA ? Vivado will be aware that those two clocks are now synchronous ? If yes then how much it will cost in terms of any clock jitter or uncertainty in STA ? Or maybe for Vivado those two clocks will be asynchronous but I can treat them as synchronous and omit CDC between RXUSRCLK and TXOUTCLK ?

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roym
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Registered: ‎07-30-2007

Since you have to use RX and TX buffer bypass for absolute minimum latency I think what you need to do is use option 1.  You can use the TX master clock to drive both RX and TX userclks and have all the rest of the RX and TX lanes adjust their userclk timing to the TX master.  This way you would have one clock driving both RX and TX fabric.

You can't use option 2 because it is incompatible with TX buffer bypass.

 




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k.rymarz
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Registered: ‎05-11-2018

Two things are still not clear for me. You wrote:

Since you have to use RX and TX buffer bypass for absolute minimum latency I think what you need to do is use option 1.  You can use the TX master clock to drive both RX and TX userclks and have all the rest of the RX and TX lanes adjust their userclk timing to the TX master.  This way you would have one clock driving both RX and TX fabric.

I was thinking of using RXOUTCLK to drive both RXUSERCLK and TXUSERCLK but you suggest to use TXOUTCLK to drive RXUSERCLK and TXUSERCLK. Is this a mistake or maybe it doesn't matter which of the two( RXUSERCLK or TXUSERCLK) I'll use ?

Regarding option 2, good to know that, thanks. Where did you found this information ? I can't find that information in XAPP 1276.

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roym
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Registered: ‎07-30-2007

 Rechecking that XAPP I see it uses FRACXO to sync the clocks instead of the TX phase interpolator like the earlier similar app.  The phase interpolator is involved in buffer bypass so it can't be used for any other function.  In the case of '1276 you could use it as well. 

In either case you would drive the buffer bypass from just one lane either TX or RX, it may not matter which but I think RX is fine and it will be available a little sooner in your reset process.




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k.rymarz
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Registered: ‎05-11-2018

Thanks you very much roym for help. As I can use XAPP 1276 then question below is still valid. Could you please help me also with that ?  

Option 2. XAPP 1276. If I understand it correctly QPLL output frequency can be controlled through SDM and thanks to this we can synchronize TXOUTCLK with any clock (in my example it will be recovered clock). How it will look like in STA ? Vivado will be aware that those two clocks are now synchronous ? If yes then how much it will cost in terms of any clock jitter or uncertainty in STA ? Or maybe for Vivado those two clocks will be asynchronous but I can treat them as synchronous and omit CDC between RXUSRCLK and TXOUTCLK ?

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roym
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Registered: ‎07-30-2007

TXOUTCLK and RXOUTCLK would be separate domains but you could use the RXOUTCLK of one lane to drive both TX and RX USERCLKs by making it the Commander  channel (switching to Commander/Cadet terminology) of the buffer bypass for both RX and TX.




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