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Voyager
Voyager
2,026 Views
Registered: ‎10-31-2016

GTwizard example is not working : Artix 7

Hello, 

 

I am trying to use SMA port. For the first test I connect Tx to Rx and use GTwizard example, but it didn't seem to work. There is no data flow and the frame is not generated. It seems that GTP port is not asserting rx_reset_done and tx_reset_done signal. 

 

for this example, I have selected shared logic core i.e. rxclock and txclock are inside the core itself.

 

vivado version: 2017.3.1

 

NOTE: Ibert debug works fine.

 

Please suggest me what can be an issue. Do I have to make some changes in the example to make it work?
this is the xdc file 

create_clock -period 6.734 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]
create_clock -period 10.000 -name drpclk_in_i [get_ports DRP_CLK_IN_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DRP_CLK_IN_P]

# User Clock Constraints


set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/CLR}]
set_false_path -to [get_pins -hierarchical -filter {NAME =~ *_txfsmresetdone_r*/D}]
################################# RefClk Location constraints #####################

## LOC constrain for DRP_CLK_P/N

set_property PACKAGE_PIN P3 [get_ports DRP_CLK_IN_N]
set_property PACKAGE_PIN R3 [get_ports DRP_CLK_IN_P]

################################# mgt wrapper constraints #####################

##---------- Set placement for gt0_gtp_wrapper_i/GTPE2_CHANNEL ------
set_property LOC GTPE2_CHANNEL_X0Y3 [get_cells tx_gtwizard_0_support_i/U0/tx_gtwizard_0_init_i/tx_gtwizard_0_i/gt0_tx_gtwizard_0_i/gtpe2_i]

set_property PACKAGE_PIN AB11 [get_ports Q0_CLK1_GTREFCLK_PAD_N_IN]
set_property PACKAGE_PIN AA11 [get_ports Q0_CLK1_GTREFCLK_PAD_P_IN]

 

thank you 

 

Best regards 

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7 Replies
Voyager
Voyager
2,011 Views
Registered: ‎10-31-2016

Re: GTwizard example is not working : Artix 7

the example with the option "include shared option in example design ", works.

 

Can some explain why? or let me know how the previous example with share option in the core is not workig.

 

thanks 

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Visitor aakerberg
Visitor
1,990 Views
Registered: ‎04-04-2018

Re: GTwizard example is not working : Artix 7

I can't tell you exactly what your issue is without more information, but in my experience, whenever RESETDONE is not asserted, it is one of the following reasons:

 

 - RX/TXUSERRDY not asserted. If you have clocks that are driven from a PLL, this should be driven to a '1' after the PLL is locked. If you are not, you can tie it high all the time, but make sure it is not floating or tied to '0'.   

 

- Missing Clocks.  Make sure all of the clocks are driven - especially the TX/RXUSERCLK/CLK2 clocks.  In some examples, Vivado may connect them for you, in others, Vivado may leave them for you to connect.  

 

- Floating (or incorrectly driven) reset signals.  Make sure all of the intermediate reset signals are driven.  TX/RXPMARESET, TX/RXPCSRESET, RXLPMRESET, EYESCANRESET, RXBUFRESET.  Depending on what options you selected in the wizard, these may or may not be connected to anything.  If you are not actively using them, then they need to be tied to '0'.  If they are tied high or left floating, RESETDONE will not complete.  

 

There is a lot of good, detailed information on resets in UG482 (https://www.xilinx.com/support/documentation/user_guides/ug482_7Series_GTP_Transceivers.pdf)

Pages 38-60, including a diagram of the reset state machine.  

 

 

Arik Akerberg, Senior FPGA Engineer
Designlinx Hardware Solutions, inc
Voyager
Voyager
1,958 Views
Registered: ‎10-31-2016

Re: GTwizard example is not working : Artix 7

Hi, 

 

Thank you for replying.

 

I removed frame generator and frame checker and tied the signal as shown in below image. I set rxslide = 0 and track_data = 1 always. 

Capture.PNG

The pin connection 

Capture.PNG

 

Even though there is no input in RX_IN pin there is a signal out at gtrxdata 

Capture.PNGCapture.PNG

I would like to know why this random data is visible in ILA?

 

Thank you 

Best regards  

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Moderator
Moderator
1,917 Views
Registered: ‎07-30-2007

Re: GTwizard example is not working : Artix 7

If you edit the IPI version of the core and call for the shared logic to be outside of the core you may then have to create the example design and add the shared logic modules back into your block design.  Are you sure you didn't drop more modules than the frame gen/check?

 

If you double click on the tx_gtwizard_0_exdes_0 what does it look like inside?

 

It also seems like you would need a reset signal input at this level of the block design.




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Voyager
Voyager
1,877 Views
Registered: ‎10-31-2016

Re: GTwizard example is not working : Artix 7

hi, 

 

I changed the setting all-inclusive and include the soft reset option. I keep valid_data_in =1 

5.PNG

 

now for the setting of GTP

 

1.PNG

2.PNG3.PNG4.PNG

 

There is a signal gt0_rxelecidle_i = lost_out which tells me if there is something connected at GTP or not. But I do not understand if there is nothing connected, why still there is a signal shown in the graph. If lost_out = 1 then there is nothing connected.

6.PNG

 

 

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Voyager
Voyager
1,872 Views
Registered: ‎10-31-2016

Re: GTwizard example is not working : Artix 7

I got the answer the line rate is 2.97 Gbps. Hence I made that change. Now when there is nothing connected I see FFFF

 

Let me know if that is correct behavior?

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Xilinx Employee
Xilinx Employee
1,861 Views
Registered: ‎11-29-2007

Re: GTwizard example is not working : Artix 7

Hello,

the RXELECIDLE is asserted when the signal amplitude goes below a threshold.

There are at least two possible reasons why you could see received signal when the RXELECIDLE is high:

1) the signal is below the threshold but the signal is still revealed by the receiver

2) you are looking at some data received in the past, that have been stored in the RXBUFFER. If you trigger on RXELECIDLE going high, please wait some USRCLK cycles before reading rxdata.

 

FFF... could mean that your rxdata are static high. it might be correct if you are not transmitting data and there is no encoder. Why not testing with a PRBS generator/checker? Please refer to https://www.xilinx.com/support/documentation/application_notes/xapp884_PRBS_GeneratorChecker.pdf