UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
459 Views
Registered: ‎12-18-2014

Generate Jitter with Transceiver

Jump to solution

Hi,

I have a chip to chip connection via GTY.

Now I want to determine the link margin of my channel.

Is it possible modulate some jitter with the transceiver? 

Currently I am evaluating PRBS pattern but it would also be helpful if I could modify some Transceiver parameters to generate Jitter!

 

I have 8b/10b @ 14Gigabit 

 

0 Kudos
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
491 Views
Registered: ‎11-29-2007

Re: Generate Jitter with Transceiver

Jump to solution

hello,

a couple of notes:

  • 8B10B encoding is a waste of bandwidth at 14Gbps.
  • if you use a PRBS pattern and then the GTY encodes it 8B10B, you will not see main differences between PRBS flavours. You should send raw data (not encoded) instead. The jitter due to different PRBS is mainly deterministic jitter (ISI), you might be interested in all other jitter components.

Usually, the margin analysis is performed with a simple eye scan and the comparison with the masks provided by Xilinx. This has already been characterized with corner cases (silicon, temperature, power supply) and the mask is the result of this job.

Your single measurement is valid only in the particular environment you are testing (Voltage and Temperature), for the specific device under test.

 

If you want to add some jitter to the transmitted signal, you could modulate the phase of the REFCLK. Please consider that the internal QPLL/CPLL will filter the low frequency modulation.

You could also drive the TXPI but I doubt the achieved phase modulation frequency is high enough and the CDR will easily track it. If your system is synchronous you might

  • set the RX CDR on HOLD
  • sweep the TXPI and see when the RX fails

 

You should also add controlled jitter to the power supplies, for a complete margin analysis.

In summary, this is not a trivial test.

 

 

 

2 Replies
Xilinx Employee
Xilinx Employee
411 Views
Registered: ‎08-07-2007

回复: Generate Jitter with Transceiver

Jump to solution

hi @sevenclock

 

commonly IBERT is the tool to evaluate link margin.

You can see the eye diagram after equalization.

 

below is the IP document.

https://www.xilinx.com/support/documentation/ip_documentation/ibert_ultrascale_gty/v1_3/pg196-ibert-ultrascale-gty.pdf

 

below is demo.

http://www.xilinx.com/support/documentation/boards_and_kits/vcu1287/2017_4/ug1203-vcu1287-ibert-gsg.pdf

 

for 8b10b you can select PRBS-7.

 

btw, it is not usual to run 8b10b at such a high linerate. why not use 64b66b? 

 

Thanks,

Boris

 

 

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Xilinx Employee
Xilinx Employee
492 Views
Registered: ‎11-29-2007

Re: Generate Jitter with Transceiver

Jump to solution

hello,

a couple of notes:

  • 8B10B encoding is a waste of bandwidth at 14Gbps.
  • if you use a PRBS pattern and then the GTY encodes it 8B10B, you will not see main differences between PRBS flavours. You should send raw data (not encoded) instead. The jitter due to different PRBS is mainly deterministic jitter (ISI), you might be interested in all other jitter components.

Usually, the margin analysis is performed with a simple eye scan and the comparison with the masks provided by Xilinx. This has already been characterized with corner cases (silicon, temperature, power supply) and the mask is the result of this job.

Your single measurement is valid only in the particular environment you are testing (Voltage and Temperature), for the specific device under test.

 

If you want to add some jitter to the transmitted signal, you could modulate the phase of the REFCLK. Please consider that the internal QPLL/CPLL will filter the low frequency modulation.

You could also drive the TXPI but I doubt the achieved phase modulation frequency is high enough and the CDR will easily track it. If your system is synchronous you might

  • set the RX CDR on HOLD
  • sweep the TXPI and see when the RX fails

 

You should also add controlled jitter to the power supplies, for a complete margin analysis.

In summary, this is not a trivial test.