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Scholar
Scholar
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Registered: ‎12-07-2018

Help with Aurora 64B/64B Example

Hello, I am using the ZCU-106 to learn how to use the Aurora 64B/66B IP. I have some questions about the input port to the IP.

The IP GT Refclk has 156.25MHz, is that the refclk1_in port? I assume it is and have connected it to a 156.26Mhz clock.

Could I connected the pma_init to the peripheral_reset port of the Processor Reset IP?

I looked through the Auroa 64B/66B IP and it's not clear to my what the port "user_clk" should be connected to can you help me with this signal?

TopBlock.jpg

Next, what should do with mmcm_not_locked? Should I connect this up to one of the Clock Wizards?

Next, what should I do with gt_qpllclk_quad_in, gt_qpllrefclk_quad1_in? I don't understand page 29 in the documentation.

Last, gt_qplllock_quad1_in, gt_qpllrefclklost_quad1_in should these be connected to init_clk?

 

Thank you very much.

Joe

 

 

 

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Scholar
Scholar
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Registered: ‎12-07-2018

I found another post that said init_clk is supposed to me an external clock input. I need to research more. Joe

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Scholar
Scholar
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Registered: ‎12-07-2018

Page 65 of the Aurora doc says, "The third phase-locked parallel clock is sync_clk. This clock must also come from a BUFG and is used to drive txusrclk port of the serial transceiver."  What is a BUFG? Is that an external input?

 

Also, is says that "Parallel clock used by the serial transceiver internal synchronization logic. Provided as the txusrclk signal to the transceiver interface. The sync_clk is twice the rate of user_clk."

How do I determine the frequency of the user_clk?

Thank you very much

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @joe306 

I believe you are using Aurora 64B66B IP with "Include Shared Logic in example Design" setting.
Since you are only using one Aurora 64B66B IP in your design , Could you please set the IP as "Include Shared Logic in core" setting.

Aurora_64b66b.png

If you configured the IP as "Include Shared Logic in core" , you don't need to care about user_clk connectivity.
Please try it on your design.

# BTW, BUFG is a global clock buffer, please read UG572 Chapter1&2 for more info.

Regards
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thank you very much for responding to my message. I made the changes as you suggested:

TopBlock.jpg

Quick question for you, I tied the init_clk pin of the Aurora to the pl_clk0 of the PS IP. What should the frequency of the init_clk port be?  When I verify the design I get the following error:

Error.jpg

I have uploaded the tcl of the design so you can regenerate the design for deeper study. The pl_clk0 output of the PS IP is 99.990005 HZ. It should be 100Mhz but is unable to achieve that value. How do I fix this problem?

Thank you very much for helping me.


Joe

Error.jpg
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Scholar
Scholar
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Registered: ‎12-07-2018

Errors.jpg

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @joe306 

You can set INIT_CLK frequency in the Aurora 64B66B IP wizard. Please see :
INIT_CLK_SETTING.png

MPSoC pl_clk0 clock frequency can be configured using MPSoC wizard , "Clock configuration" tab.
If you have difficulty on PS side, please post a question on Embedded board, not here.

MPSOC_CLOCK.png

Regards
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thanks for responding to my message. I did change the INIT_clk to 99.990005 in the Aurora IP this matches the pl_clk0 output of the PS.

Aurora1.jpgAurora2.jpgAurora3.jpg

Should I use 161132813 as the pl_clk0 frequency and he INIT_clk frequency instead of 99.990005?

Thank you very much.

Aurora3.jpg
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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello

Your Aurora 64B66B IP configuration has RX data output with 161.1328125 MHz clock.
So, Yes you can either configure AXI_DMA with 161.1328125 MHz AXI clock or use FIFO to solve this issue.


Thanks
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thank you very much for responding to my post. Would you be so kind to tell me how you calculated the RX rate? I see that 161.1328125 = 10.3125 x 156.25 but the units don't work out.

161.1328125x10^6 cycles/sec
Line Rate 10.3125x10^9 bits/sec
GT Ref Clk 156.25x10^6 cycles/sec

Sorry for being slow here, can you show the calculation please?

You mentioned that I have two options. If configure the AXI_DMA for 161.1328125Mhz is that simply having the m_axi_s2mm_aclk to 161.1328125Mhz?

The second option is to use a FIFO, is that a AXI_FIFO?

Thank you very much for taking time to help me.

Joe

 

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, being a newbie here and slow, which option should I try?  I don't have to run that fast. I could have the data rate much slower. I'm only trying to do a loop back test on the SFP connector.

Thank you

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Scholar
Scholar
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Registered: ‎12-07-2018

Top BlockTop Block

Maybe this diagram will help.

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, I added the FIFO and I also added a Clock Wizard to generate the init_ref clock and also the clock for the DMA.

FIFO.jpg

Updated Top BlockUpdated Top BlockVerify ErrorsVerify Errors

The IP shows the init_clk rate should be between 3.125 - 161.132812 MHZ. I decided to try 161.132812Mhz which is generated by the Clock Wizard:

Aurora IPAurora IP

I am still getting some Verify Error messages that I hope some one can help me clear up.

I used a Clock Wizard to generate the 161.132812 and connected it to the init_clk of the Aurora IP and also the the mm2s_aclk and s2mm_aclk of the DMA. I thought these clocks need to be tied together but not sure.

I have uploaded the TCL of my design so the design can be regenerated.

Thank you very much,

Joe

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Joe,

1. I can see the error message is still the same since the frequency is different between these modules. You need to fix this.
      /axi_dma_0/S_AXIS_S2MM(161132812) and
     /aurora_64b66b_0/USER_DATA_M_AXIS_RX(161132813)

2. Clock freq calculation  is
    10312.5/64=161.1328125 MHz

3. Or as an alternative you can check the frequency configuration value on the schematic.    FREQ_BD.png

4. Yes you can simply put the same 161.1328125 MHz to your AXI_DMA module.

5. Instead if using an asynchronous ps_clk0 as a clock source (which is generated from PS_REF_CLK),
    We suggest to use usr_clk_out from Aurora 64B66B itself. You can connect it to AXI_DMA S2MM clock port.

    usr_clk_out.png

Thanks
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Thank you very much for your detailed response.

I have connected the user_clk_out to the AXI DMA m_axi_s2mm_aclk port.

What should m_axis_mm2s_aclk port be connected to?

Thank you

Joe

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, I have made some progress. I removed the Clock Wizard and am driving the init_clk from the pl0_clk (99.990005) from the PS block. I connected the user_clk_out to the DMA block, the Smart Connect Block and the AXI Data FIFO.

Now I only have the following error message:

Verify ErrorsVerify Errors

I'm not sure how to fix this error message. It is the AXI link from the AXI Data FIFO to the Slave AXI input on the PS IP.

TopBlock.jpg

 

Thank you very much for helping me get rid of these errors.

Joe

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, well I'm making progress. I just need to think like an engineer. Here is by diagram:

Presentation1.jpg

I only get the following Verify message:

Errors.jpg

How do I handle this type of message?

TopBlock.jpg

Thank you very much for all your help.

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Joe,

This is a Critical Warning. You need to fix it.
I believe the bus data-width is difference between those modules.

Currently your m_axis_mm2s_tdata is 32 bit, you need to configure it as 64bit to match Aurora 64B66B IP interface.

data_width_is_32bit_please_make_it_64.png

Please change "Stream Data Width" setting to 64 bit in the wizard.
GUI_stream_data_width.png

Thanks
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, and thank you for responding to my message and the included images. That solved my problem.

Now onto entering my Timing Constraints.

Fortunately I have an example in the Aurora documentation.

Thank you,

Joe