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443 Views
Registered: ‎10-30-2019

How to enable OOB signalling

Hello,

I am trying to use GTH Ultrascale PMA for PCIe Protocol.

I want to use Electrical Idle signalling and I am able to control TXELECIDLE and it actually stops data in the serial line.

I am facing the issue with RXELECIDLE, I have put RXELECIDLEMODE = 2'b00 but there is no toggling of RXELECIDLE it stays high even though there is activity in the serial link (Line rate 2.5GT/s and 5.0GT/s).

I am suspecting that OOB_PWRUP attribute is set to 1'b0 because while generating the IP I was not able to select OOB signalling by clicking the box(it is basically disabled)

The reference clock is 100MHz and line rate is 5.GT/s with no encoding(raw data).

So how to enable OOB signalling?

Regards,

Saket

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5 Replies
Visitor cm16xilinx
Visitor
412 Views
Registered: ‎10-07-2016

Re: How to enable OOB signalling

Add to the xdc file

# To enable XCVR Rx EI detection functionality
set_property OOB_PWRUP 1 [get_cells -hierarchical -filter {NAME =~ "*GTY_INST*" && NAME =~ "*gen_channel_container*" && NAME =~ "*GTYE4_CHANNEL_PRIM_INST*"}]
set_property RXOOB_CLK_CFG FABRIC [get_cells -hierarchical -filter {NAME =~ "*GTY_INST*" && NAME =~ "*gen_channel_container*" && NAME =~ "*GTYE4_CHANNEL_PRIM_INST*"}]

 

if you need for simulation too, add to the testbench

defparam DUT.XCVR.GTY_INST.inst.gen_gtwizard_gtye4_top.GTY_x4_20_625G_gtwizard_gtye4_inst.gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst.channel_inst.GTYE4_CHANNEL_OOB_PWRUP = 1;
defparam DUT.XCVR.GTY_INST.inst.gen_gtwizard_gtye4_top.GTY_x4_20_625G_gtwizard_gtye4_inst.gen_gtwizard_gtye4.gen_channel_container[32].gen_enabled_channel.gtye4_channel_wrapper_inst.channel_inst.GTYE4_CHANNEL_RXOOB_CLK_CFG = "FABRIC";

Visitor cm16xilinx
Visitor
410 Views
Registered: ‎10-07-2016

Re: How to enable OOB signalling

Forgot, on the testbench defparam,  modify the path to match your design

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325 Views
Registered: ‎10-30-2019

Re: How to enable OOB signalling

Thanks for the reply, @cm16xilinx

I was able to check the functionality of RxElecidle in TB simulations and the functionality was as intended (Used defparam to change parameter value).

Can you please explain to me how the XDC command given by you will work when we put the RTL in the FPGA board? or what does this command do? CHANNEL_PRIM_INST is only a parameter file. So how does the XDC tell the design or FPGA that OOB_PWRUP needs to be 1?

I am not able to understand the actual effect of the code given by you in the FPGA board (I am new to the FPGA and Synthesis kind of things also I ran synthesis after putting the command given by you in XDC for OOB_PWRUP and synthesis and implementation goes through fine).

set_property OOB_PWRUP 1 [get_cells -hierarchical -filter {NAME =~ "*GTY_INST*" && NAME =~ "*gen_channel_container*" && NAME =~ "*GTYE4_CHANNEL_PRIM_INST*"}]

 

Regards,

Saket

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Visitor cm16xilinx
Visitor
302 Views
Registered: ‎10-07-2016

Re: How to enable OOB signalling

Basically when you configure the GTH with the GUI, you are defined setting that gets hardcoded as ports values or preloaded into internal configuration registers of the GTH Hard IP.

With defparam you overwrite the default value assigned by the GUI, with set_property you do the same but the value change is applied during implementation.

In my example I set defparam for simulation in the testbench, I never tried to put instead within the design, if works then you do not need to do it too in the xdc

If your design include DRP interface, you could also read and change these register value too.

For these registers you can search for RXOOB_CLK_CFG and OOB_PWRUP in the ug576-ultrascale-gth-transceivers.pdf.

The example I gave was from my design which uses GTYE4 and has instance name I assigned,  you have to find which is the correct path and names for your GTH.

An easy way is to open the synthesized design schematic and dig down in the hierarchy until you reach the GTH primitive, then from the property windows you should get the correct path and property names.

Highlighted
115 Views
Registered: ‎10-30-2019

Re: How to enable OOB signalling

Hi @cm16xilinx ,

set_property option for setting up OOB_PWRUP doesn't work in the board.Maybe because XCI is not allowing this change or maybe something else.

Although the defparam option works in simulation.

Thanks for the help

 

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