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jiongsi
Observer
Observer
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Registered: ‎07-02-2019

How to run IBERT test on two AC701 boards

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I need run IBERT test on two AC701 boards,

1. how should I connect the PMA cables?

TX_P1->TX_P2, TX_N1->TX_N2,  RX_P1->RX_P2, RX_N1->RX_N2?

OR

TX_P1->RX_P2, TX_N1->RX_N2,  TX_P2->RX_P1, TX_N2->RX_N1?

2. which loopback mode should I choose?

3. do I need to assign TX/RX pins of the IBERT IP design to FPGA pins?

Thanks a lot.

 

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eschidl
Xilinx Employee
Xilinx Employee
774 Views
Registered: ‎10-19-2011

Hi @jiongsi ,

your second connection approach is correct, TX1->RX2 and TX2->RX1.

as you have a direct connection you do not need to set any loopback.

If you selected the correct transceiver/quad when generating the IBERT design, the transceivers will be placed correctly and you do not need to set anything for the TX/RX data pins. Check the reference clock and system clock setup though.

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eschidl
Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @jiongsi ,

your second connection approach is correct, TX1->RX2 and TX2->RX1.

as you have a direct connection you do not need to set any loopback.

If you selected the correct transceiver/quad when generating the IBERT design, the transceivers will be placed correctly and you do not need to set anything for the TX/RX data pins. Check the reference clock and system clock setup though.

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jiongsi
Observer
Observer
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Registered: ‎07-02-2019

@eschidlthank you for your reply.

Both boards work well when I set the TX/RX Pattern as PRBS 7-bit on both boards,and both boards can receive the other one's error inject.

But one boards doesn't work (there are a lot of Errors) if I set TX/RX Pattern to other bits.

Does the TX/RX Patterns matter?

Annotation 2019-11-13 091935.png

 

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eschidl
Xilinx Employee
Xilinx Employee
735 Views
Registered: ‎10-19-2011

Hi @jiongsi ,

yes, you need matching pattern at both sides. The TX should send the same pattern that the RX expects, Otherwise error testing would not make sense.

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jiongsi
Observer
Observer
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Registered: ‎07-02-2019

Hi @eschidl ,

Yes, I changed every TX/RX on both boards to the same PRBS pattern, but still one board works, the other always has errors.

I found PRBS 7-bit pattern also has occasional errors.

Fast Clk and Slow Clk patterns don't have errors so far.

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eschidl
Xilinx Employee
Xilinx Employee
641 Views
Registered: ‎10-19-2011

Hi @jiongsi ,

can it be that you use the EPHYCLK of the board as reference clock for a 6.25Gbps link? This is meant for 1G Etherent connections. If yes, can you try to use the SMA reference clock connection with an external clock generator or the jitter attenuator?

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jiongsi
Observer
Observer
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Registered: ‎07-02-2019

Hi @eschidl ,

I am not sure what's EPHYCLK... here is my clock settings:

1.PNG2.PNG

I don't have an external clock generator, can only use the on board oscillator.

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eschidl
Xilinx Employee
Xilinx Employee
621 Views
Registered: ‎10-19-2011

Hi @jiongsi ,

check with UG952, page 25 for the clocking. You will see the EPHYCLK there. It is the on board 125MHz clock.

Could you borrow a clock generator and use the SMA refclk input then?

Or could you try a lower line rate?

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