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Visitor
Visitor
213 Views
Registered: ‎08-01-2020

How to use/connect 2 different clocks in the same GTH bank - Ultrascale+

Hi All,

In my design i use Ultrascale+ and i need to output 2 videos standard from the same bank(in 106 EV board is bank 225):
1. SDI - 148.5MHz.
2. CXP - 125MHz.

Questions:
1. which cores i need to use?
2. how looks the architecture of this design?
3. how i disable the RX channel? (in the Transcivers wizrad)

Best Regards,

AvivY

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Xilinx Employee
Xilinx Employee
141 Views
Registered: ‎03-30-2016

Hello @AvivY 

I don't think anyone has a quick answer for your questions.
If both of those IPs are using QPLL, sharing GTH quad is not possible,
But if one of those IP is using CPLL, perhaps sharing GTH quad is possible, but you definetely need to build a test design to ensure.

Xilinx offer the following UHD-SDI Subsystem IP for UltraScale+ GTH.
https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi/v1_0/pg205-v-smpte-uhdsdi.pdf
https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_tx_ss/v2_0/pg289-v-smpte-uhdsdi-tx-ss.pdf
https://www.xilinx.com/support/documentation/ip_documentation/v_smpte_uhdsdi_rx_ss/v2_0/pg290-v-smpte-uhdsdi-rx-ss.pdf

Please check those documents and do some experiment with the IP wizards,
to see if your IP usecase is implementable with CPLL.

# BTW, what is CXP ? I am not aware if Xilinx has CXP IP.

Regards
Leo