07-31-2019 11:44 AM
I'm trying to generate a system using the GTY wizard and have enabled the DRP I/O ports. However, there doesn't seem to be any documentation on how the ports are supposed to be accessed. They're 16-bit data ports but on the top level example design they're concatenated together and the only Microblaze example I can find has a 16-bit DRP port (that's the MCS so perhaps not meant for use with GTYs?).
Are there any example systems that detail how to hook this up? The I/O Module IP block looks semi suitable but again doesn't have the correct data width. Is the use case for this that the end user is supposed to generate their own address mapped peripheral to map to the 5 DRP ports?
07-31-2019 02:20 PM
I find it easy enough to program what ever changes I need using RTL code to manipulate the ports as described in UG578 - see the drp section starting on page 88 and the write and read timing on page 88 and 89. There is a DRP address map in the appendix where you find the addresses to use.
If your not good with RTL and prefer the microblaze XAPP746 runs the drp port with a microblaze to do Eye Scans. You should be able to leverage that example code though it seems harder to me.
08-01-2019 12:41 AM - edited 08-01-2019 12:48 AM
I'm happy writing the RTL but this is a solved problem and I would have thought there was a Microblaze example system or at least guidance. The IBERT core has a Microblaze internally so Xilinx themselves are doing this.
I don't need to reinvent the wheel for what should be a simple IP hookup job.
Edit: the XAPP you mentioned doesn't exist if I search for it. Typo?
08-01-2019 03:07 AM - edited 08-01-2019 03:08 AM
Hi firstname.lastname@example.org ,
Roy probably meant xapp743, and I think that is the same you looked at before. You might just need to adjust the address width and maybe build a select depending on which CHANNEL/COMMON you want to address.
Regarding the port connectivity for the DRP on the wizard core, did you have a look at pg182? There it is described that the port width changes depending on the lanes used in the core. "The width of each port scales with the number of transceiver channel primitives instantiated within the core instance. The least significant bit(s) correspond to the first enabled transceiver channel primitive in increasing grid order, where the Y axis increments before X."
E.g. page 39 you find the DRP ports for the CHANNEL described (e.g.: drpaddr_in -> Input -> drp_addr_width x Num. Channels)