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memset
Contributor
Contributor
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Registered: ‎12-23-2009

How to use the same TX clock domain on different sides of ultrascale chip?

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Hello, all!

It's known what it's not possible to internally share an GTY REFCLK between GTY quads on the Right and Left sides of the chip. Also, sharing is not possible between GTY quads on the same side, but in different SLRs.

I want to use one single TX clock domain for multiple 10G/25G Ethernet interfaces on both sides of Ultrascale+ chip. Is it possible? I plan to fanout my REFCLK from the same source into several copies (via any low-jitter clock buffer) to feed several MGTREFCLK inputs on different sides of the chip (optionally these copies can be length-matched).

- If the same external REFCLK would be used to feed different sides of the chip, is it possible to use TX OUT clock from a single GTY  as a common TX fabric clock for several quads on different sides of the chip?

- If yes, do I need to provide a phase-matching between several copies of external REFCLK source?

- If yes, is it possible to use GTY configuration with bypassed TX buffers?

 

Thanks in advance!

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roym
Moderator
Moderator
134 Views
Registered: ‎07-30-2007

You can use one TX usrclk domain between different sides of the chip provided the refclk is copied in the manner you describe (rooted to the same oscillator).  

Buffer bypass should work as well although it would not be as robust a solution as using the buffer.  There are potential jitter problems with the TXUSRCLK fanned out like that in buffer bypass mode especially at the highest frequencies.  I always recommend using the TX buffer if it is possible.

 

 




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1 Reply
roym
Moderator
Moderator
135 Views
Registered: ‎07-30-2007

You can use one TX usrclk domain between different sides of the chip provided the refclk is copied in the manner you describe (rooted to the same oscillator).  

Buffer bypass should work as well although it would not be as robust a solution as using the buffer.  There are potential jitter problems with the TXUSRCLK fanned out like that in buffer bypass mode especially at the highest frequencies.  I always recommend using the TX buffer if it is possible.

 

 




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
Be sure to visit the Resources post periodically to keep up with the latest
https://forums.xilinx.com/t5/Serial-Transceivers/Serial-Transceiver-Forum-Guidelines-and-Useful-Resources/td-p/1173590
----------------------------------------------------------------------------


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