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Contributor
Contributor
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Registered: ‎03-06-2016

I want to use a single reference clock to drive 16 gth lanes

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Hi:
I have an ad9213 reference board,the ad9213's sampling rate is up to 10GSPS. we want to connect all the 16 lanes to V7 690T fpga. However the GTH transceiver wizard shows that we can only select 12 lanes when we select the jesd204b configuration preset for a single reference clock. the jesd204b phy ipcore supports at most 12 lanes. From the gth user guide,the qpll reference clock can only drive 3 gth quad.
Is it possible to select 16 lanes for a a single reference clock? Thanks a lot.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: I want to use a single reference clock to drive 16 gth lanes

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Hi @gauss_work ,

if you give PG066, figure 3-2 a look, you can see that every clock in a JESD204B setup is actually synchronous. Your second refclk coming in would just be another parallel buffer to the first one with the same source.

So in fabric you could actually use the same clocks for both cores.

For the reference clocks you should take care that they are clean and follow the requirements from the datasheet and AR44549.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: I want to use a single reference clock to drive 16 gth lanes

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Hi @gauss_work ,

no, this is not possible on 7 series transceivers. You can only drive one quad up and one quad down, which gives you 12 lanes max from one single reference clock.

You will need to buffer the reference clock on the board to drive two reference clock inputs to reach 16 lanes.

You can then generate two 8 lane JESD cores which you can combine to support 16 lanes from the ADC.

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Contributor
Contributor
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Registered: ‎03-06-2016

Re: I want to use a single reference clock to drive 16 gth lanes

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@eschidl,thanks for your reply.but if we use two reference clocks and two jesd204b ipcores, we will get 2 axis clock.s
how can we sync two axi streams to one single user clock? For the hardware design,what special we should pay attention to for the two reference clocks? like jitter or phase difference?

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: I want to use a single reference clock to drive 16 gth lanes

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Hi @gauss_work ,

if you give PG066, figure 3-2 a look, you can see that every clock in a JESD204B setup is actually synchronous. Your second refclk coming in would just be another parallel buffer to the first one with the same source.

So in fabric you could actually use the same clocks for both cores.

For the reference clocks you should take care that they are clean and follow the requirements from the datasheet and AR44549.

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View solution in original post

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Adventurer
Adventurer
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Registered: ‎01-21-2012

Re: I want to use a single reference clock to drive 16 gth lanes

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To implement the 16-lane AD9213 interface, is this picture correct?AD9213 JESD Scheme.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: I want to use a single reference clock to drive 16 gth lanes

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Hi @kendrick ,

there is no common QPLL clock possible between the PHYs.

Each PHY will need its own reference clock coming in from external.

The MGT clock in your drawing will then be one of these reference clocks.

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Adventurer
Adventurer
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Registered: ‎01-21-2012

Re: I want to use a single reference clock to drive 16 gth lanes

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Is it this then? Two completely independent paths? If so, what is the mechanism for synchronizing the two? Do I need to ensure that the two MGT clocks are in phase? The source of the MGT clocks is an HMC7044 chip.

AD9213 JESD Scheme 2.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: I want to use a single reference clock to drive 16 gth lanes

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Hi @kendrick ,

no, please check the solution for this thread.

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