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vhdlveri123
Explorer
Explorer
404 Views
Registered: ‎04-21-2021

IBERT Core not detecting

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H,

I am trying to debug using the IBERT , but when i programmed the device, the IBERT core is not detected. I used in_system_ibert , the free running frequency is derived from the reference clock as shown below. The error was that the DRP clock may not be given. Why is this?


IBUFDS_GTE3 #(
.REFCLK_EN_TX_PATH (1'b0),
.REFCLK_HROW_CK_SEL (2'b00),
.REFCLK_ICNTL_RX (2'b00)
) IBUFDS_GTE3_MGTREFCLK0_X0Y3_INST (
.I (mgtrefclk0_x0y3_p),
.IB (mgtrefclk0_x0y3_n),
.CEB (1'b0),
.O (mgtrefclk0_x0y3_int),
.ODIV2 (hb_gtwiz_reset_clk_freerun_in)
);


wire hb_gtwiz_reset_clk_freerun_buf_int;


BUFG_GT bufg_gt_freerun_buf_int (
.CE (1'b1),
.CEMASK (1'b0),
.CLR (hb0_gtwiz_reset_all_int),
.CLRMASK (1'b0),
.DIV (3'b000),
.I (hb_gtwiz_reset_clk_freerun_in),
.O (hb_gtwiz_reset_clk_freerun_buf_int)
);

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ghasemi_r
Explorer
Explorer
324 Views
Registered: ‎05-07-2018

change the DRP clock in your setup, 

use an existed clock on your board, not the clock that comes from IBUFDS_GTE3

make sure clock is definitely present.

also, it may happen because of some hardware problems.

View solution in original post

3 Replies
roym
Moderator
Moderator
391 Views
Registered: ‎07-30-2007

I've always used the instantiation below successfully.  Make sure the constraints file is putting the refclk on the pins you expect.  Somewhere above you should have made the *freerun_in a wire.

BUFG_GT bufg_gt_freerun_buf_int (
.I (hb_gtwiz_reset_clk_freerun_in),
.O (hb_gtwiz_reset_clk_freerun_buf_int)
);




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vhdlveri123
Explorer
Explorer
341 Views
Registered: ‎04-21-2021

Hi,

i made the freerun as a wire. I initially did what u said. Then there were problems showing about routing.

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ghasemi_r
Explorer
Explorer
325 Views
Registered: ‎05-07-2018

change the DRP clock in your setup, 

use an existed clock on your board, not the clock that comes from IBUFDS_GTE3

make sure clock is definitely present.

also, it may happen because of some hardware problems.

View solution in original post