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Visitor
Visitor
443 Views
Registered: ‎01-15-2020

IBERT+ and Zync7000 GTX

I am using a Z7035 part and I would like clarification on device support for AR#70915. In the AR the document suggests that only GTH transceivers are supported in the IBERT+ flow. Looking at the referenced XAPP1322  it states that GT debugger will support Series 7 devices. I am having trouble once I get to the "Vector Eyescan and margin analysis" steps (EyeQualification doc) as I receive this error:

 

source ./insert_gt_dbg/igd_eyescan.tcl

igd_eyescan init cX0Y13

WARNING: [Labtoolstcl 44-226] No matching hw_axi were found

ERROR: [Common 17-55] 'get_property' expects at least one object.

Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.

When I look at the HW manager window I do not see hw_axi core listed under the device and as I examine the example IBERT design I do not see any dbg_hub instantiated in the schematic (this however is found in a kintex ultrascale example IBERT design). Does the GT Debugger support Zync 7 series parts and therefore GTX transceivers? Do I need to instantiate anything to the example design and .dcp to proceed with eye qualification?

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: IBERT+ and Zync7000 GTX

Hi @mphanav ,

the scripts should work on 7 series GTX.

So you run through the analyse and modify steps successfully and you do not see the hw_axi detected in HW manager?

Is the IBERT design by itself working correctly?

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Visitor
Visitor
348 Views
Registered: ‎01-15-2020

Re: IBERT+ and Zync7000 GTX

Hi @eschidl ,

Thanks for the confirmation. You are correct that I do not see the hw_axi detected in HW manager and the IBERT design itself is working correctly (sweeps/scans/etc). If you instantiate the example IBERT design from Xilinx you should be able to see the same thing.

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Xilinx Employee
Xilinx Employee
330 Views
Registered: ‎10-19-2011

Re: IBERT+ and Zync7000 GTX

Hi @mphanav ,

did you choose a free running clock for the debug clock?

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Visitor
Visitor
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Registered: ‎01-15-2020

Re: IBERT+ and Zync7000 GTX

Hi @eschidl ,

 

Yes I did enable the dclk. See below:

 

[section clock]

use BUFG/DBG_HUB Frequency Buffer output net
________________________________________________________________________________________________________________________________________________________
(If DBG_HUB is present, its input clock should be used. Otherwise debug cores might not be detected.)
y u_ibert_core/inst/SYSCLK_DIVIDER.u_bufg_dclk 100.000 MHz u_ibert_core/inst/dclk
n u_ibert_core/inst/SYSCLK_DIVIDER.u_pre_bufg 200.000 MHz u_ibert_core/inst/sysclk_int_temp

 

I've actually tried both clocks and neither of them works in bringing up the hw_axi core.

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Newbie
Newbie
257 Views
Registered: ‎04-05-2019

Re: IBERT+ and Zync7000 GTX

Hi,

 

Do you have any update on this?

 

Thanks

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Xilinx Employee
Xilinx Employee
237 Views
Registered: ‎10-19-2011

Re: IBERT+ and Zync7000 GTX

Hi @mphan ,

when you open the checkpoint after insertion (post_igd_hila.dcp), do you see the debug logic added to the design (ibg_bd_jtag2axi2drpgpio) and a dbg_hub inserted?

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Visitor
Visitor
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Registered: ‎01-15-2020

Re: IBERT+ and Zync7000 GTX

Yes, we can see the debug logic added in both the post_igd_hila.dcp and igd_impl.dcp checkpoints.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: IBERT+ and Zync7000 GTX

Hi @mphanav,

I think you might have gotten the information already. I just wanted to give the solution here too.

The IBERT design and the other debug cores are connected to different scan chains, which would need to be scanned after configuration for the core detection. The default changed for the chains looked at, it seems. It was chains 1 and 3 before. Now only chain 1 is scanned. This can be solved with the following:

 
 
 

image.png

If BSCAN_SWITCH_USER_MASK comes per default up as 0001, you need to change it to the above value before configuring the device to see both scan chains.
If there are more chains in your design you need to enable these too, of course.

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