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Registered: ‎03-07-2019

IBERT system clock in clock setting

I am using Genesys-2 Kintex-7 [1] FPGA board for BER measurement. I am using IBERT available in IP catalogue of Vivado. Genesys-2 has an FMC connector to provide output for which I am using [SMA-FMC-LVDS][2] of Hightech Global to convert the data from FMC to SMA. Initially, I am connecting transmitter and receiver in loopback just for verification.

The problem is:
1. In loopback connection, in Vivado I am unable to see any transmission. It is only displaying 0Gbps.

2. Previously I have used different [SMA-FMC][3] board for which transmission was proper and I was able to measure the BER for the same code.

3. In the [SMA-FMC-LVDS][2] a place holder is provided for an external oscillator. Do I need to solder this oscillator for proper transmission?

4. Can I use the internal clock (QUAD Clock) as a clock source for the system clock in the clock setting when IBERT? Picture is attached. 

5. For system clock, if we use external as a source for the clock, from where this clock will come from. DO the external oscillator on [SMA-FMC-LVDS][2] board will provide this clock?



system clock.png
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Registered: ‎07-30-2007

For the GT to work you have to have a refclk input.  I always use the refclk as the system clock to avoid any issues and delays getting the system clock set up correctly.  Choose the source as internal and then you will be able to choose whichever refclk is live in your system.

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