10-22-2018 06:17 AM
We have multiple PCB board designs on which we use the zynq 7000 series.
On a few boards we use the bank 111 transceivers for our 10G connections and on a few others we use bank 112 for that.
On the designs which have the 10G connected to bank 112 the IBERT functionality works as expected but on the designs with the 10G connected to bank 111 we observe the following issues:
- Auto-detect links does not detect any links.
Manual creating the links:
- Near End-PCS loopback does work
- Near End-PMA does work sometimes (it looses link every now and then)
- Far End-PCS does not work
- Far End-PMA does not work
- None does not work
All above does work on the other boards on bank 112.
is this a known issue and what should I change on the configuration?
10-22-2018 08:58 AM
can you let us know what is RX Equalizer used for both the cases and what is the value of TXBUFDIFFCTRL.
10-22-2018 09:36 AM
In addition to potential problems with NE-PMA with DFE mode equalization as Chandra is hinting at, it is not clear to me that you understand that if you put the gt in your device in far end loopback mode that you won't get any data. You have to put the far-end device in far-end loopback for your gt to have good input data.
In the bank that doesn't work at all you should double check all the IO ports in the IO report and make sure they are routed where they should be.
10-22-2018 09:40 AM
Can you tell me where I can found those values?
If I look into my implemented design the TXBUFDIFFCTRL is connected to a register. Is that the "TX Diff Swing" setting in Vivado Lab edition? This is set to 0x1100 (1018mV) but I tried different values with no success.
The Rx Equalizer I cannot find at all.
10-22-2018 11:04 AM
Hello Roy and Chandra,
I was wrong. In both Far-End PMA an PCS mode it is "not working" for all my designs. As mentioned by Roy the Far End device is not set to loopback.
At the moment I am mostly interested in the "none" option where I used a fiber as loopback.
I've got some interesting finding regarding the used pinning when I open the implemented design. Although the xci, the ip configuration and the wrapper file mention it should be on bank 111, the implemented designs shows that the pinning is connected to bank 112. I will dig into this further but this can explain why it does not work.