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Voyager
Voyager
3,253 Views
Registered: ‎07-28-2008

IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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I am looking at sharing reference clocks between multiple QUADs, the same clock after IBUFDS_GTE4 to drive a lot of generic logic.

 

Don't know if this is a good idea or not.

 

I read from UG576, there are rules in limiting number of transceivers in using the reference clock.

 

Please comment.

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Moderator
Moderator
4,141 Views
Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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You cannot use the ODIV2 output of IBUFDS_GTE4 to drive general logic without using BUFG_GT. This clock buffer takes the reference clock to global clock routing.

The limitation mentioned in ug576, is related to the clock route driven by "O" output of IBUFDS_GTE4. This clock route is only used for driving transceivers. This is different from the global clock route driven by the ODIV2 output of IBUFDS_GTE4.
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Moderator
Moderator
4,142 Views
Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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You cannot use the ODIV2 output of IBUFDS_GTE4 to drive general logic without using BUFG_GT. This clock buffer takes the reference clock to global clock routing.

The limitation mentioned in ug576, is related to the clock route driven by "O" output of IBUFDS_GTE4. This clock route is only used for driving transceivers. This is different from the global clock route driven by the ODIV2 output of IBUFDS_GTE4.
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Voyager
Voyager
3,242 Views
Registered: ‎07-28-2008

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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pg210.PNG

 

It seems gt_refclk_out is after BUFG_GT, is it possible to bring out refclk to be used by other QUAD, without changing 10G/25G subsystem core structure in a block design?

 

Thanks,

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Moderator
Moderator
3,234 Views
Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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gt_refclk_out is the output of IBUFDS_GTE4 buffer. You will only tap it on the same quad, in which the clock is supplied.
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Moderator
Moderator
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Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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I was referring to ODIV2 output in my previous post below.

=================
gt_refclk_out is the output of IBUFDS_GTE4 buffer. You will only tap it on the same quad, in which the clock is supplied.
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Voyager
Voyager
3,213 Views
Registered: ‎07-28-2008

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Great thanks,

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Voyager
Voyager
3,170 Views
Registered: ‎07-28-2008

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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I have a design passed implementation.

 

It has QUADs taking reference clock from 10G.gt_refclk_out (which is output of BUFG_GT), also the clock is used by generic logic.

mgt_refclk_sharing.PNG

 

Is there any risk/increased jitter on my GT Quads to use this clock as reference input?

 

Regards,

 

 

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Moderator
Moderator
3,163 Views
Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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This usage has been followed by many customers. There is no issue with it.
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Moderator
Moderator
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Registered: ‎02-16-2010

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Just want to clarify your usage. Can you please confirm?
I understand that you are using "ODIV2" for fabric logic and "O" for multiple quads.
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Explorer
Explorer
1,592 Views
Registered: ‎04-21-2017

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Dear Forum,

Can this solution be setup using the Buf_Util blocks in the Vivado IPI, or does it require Verilog/VHDL instantiation? I have Util-buffers configured as IBUF-GTE feeding BUFG_GT, but no clock is getting to the logic.

MPSoC-MGT-2-Fabric.png

TTFN.

DJE666

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Explorer
Explorer
1,587 Views
Registered: ‎04-21-2017

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Schematic looks ok.....?

gte4_2_bufg_gt-sch.pngI Think....

 

DJE666

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Adventurer
Adventurer
1,343 Views
Registered: ‎07-27-2018

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Hi dje666,

I think you are near the solution, simply don't put all other signals of the ds_buf to ground.

Take a look at this post:

https://forums.xilinx.com/t5/Serial-Transceivers/Zynq-Ultrascale-SMA-MGT-Clock-input/td-p/855914

Based on that simply put some constant block IP to give the right settings

connections.png

Best Regars.

 

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Visitor likith
Visitor
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Registered: ‎01-04-2019

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Can we drive the gt_ref_clk from IBUFDS_GTE4 to BUF_GT and then we can share ' O' ref_clk to other logic blocks?

beacuse i finding some issues like this...

 

[DRC REQP-1929] IBUFDS_GTE4_O_may_only_drive_GTxE4: The IBUFDS_GTE4 n10g_interface_inst/IBUFDS_GTE4_inst O pin may only be connected to the GTREFCLK pin of a GTHE4_COMMON, GTHE4_CHANNEL, GTYE4_COMMON, or GTYE4_CHANNEL component. The IBUFDS_GTE4 O pin cannot drive n10g_interface_inst/xgbaser_gt_wrapper_inst/bufhce_156_25_inst, and n10g_interface_inst/xgbaser_gt_wrapper_inst/i_ten_gig_eth_pcs_pma_ip_common_wrapper/ten_gig_eth_pcs_pma_ip_gt_gtye4_common_wrapper_i/common_inst/gtye4_common_gen.GTYE4_COMMON_PRIM_INST.

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Re: IBUFDS_GTE4 output drive generic logic, would it introduce jitter?

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Hi @likith ,

you are replying to an old thread with a new topic. It would be better to open a new thread to get an answer.

If you look at ug576, page 25, you can see that the 'O' output in the IBUFDS_GTE4 can only drive *COMMON or *CHANNEL primitives. So the DRC message is correct if you try to connect it to a BUFG_GT.

Only the 'ODIV2 ' output has routings to BUFG_GT and can therefor drive fabric logic. With REFCLK_HROW_CK_SEL you can select what you will see at the output.

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