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Visitor
Visitor
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Registered: ‎11-04-2019

IBUFDS error in Virtex 6 GTX

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Hi,

I'm currently trying to implement the GTX transceiver in my ML605 using the differential clock from the board oscilator as reference clock. Here is my ucf:


CONFIG PART = XC6VLX240T-FF1156-1 ;

NET "SYSCLK_P" LOC = J9 | IOSTANDARD = LVDS_25;
NET "SYSCLK_N" LOC = H9 | IOSTANDARD = LVDS_25;

 

## Timing Constraints...
NET "SYSCLK_P" TNM_NET = "SYS0CLKP"; # 200 MHz sys0 XO
TIMESPEC "TS_SYS0CLKP" = PERIOD "SYS0CLKP" 200 MHz HIGH 50 % ;

NET "SYSCLK_P" TNM_NET = "SYS0CLKN"; # 200 MHz sys0 XO
TIMESPEC "TS_SYS0CLKN" = PERIOD "SYS0CLKN" 200 MHz HIGH 50 % ;

INST gtx_TX_i/gtx0_gtx_TX_i/gtxe1_i LOC = GTXE1_X0Y18;
INST clkbuf1 LOC = IBUFDS_GTXE1_X0Y0;
NET "tx_n" LOC = "B2";
NET "tx_p" LOC = "B1";
NET "rx_n" LOC = "D6";
NET "rx_p" LOC = "D5";

And my verilog top module:

IBUFDS_GTXE1 #
(
.CLKRCV_TRST ("TRUE"),
.CLKCM_CFG ("TRUE")
)clkbuf1 (
.O (clk_in150),
.I (SYSCLK_P),
.IB (SYSCLK_N),
.CEB (tied_to_ground_i)
);

With clk_in150 to :

gtx_TX_i
(

.GTX0_MGTREFCLKTX_IN (clk_in150),

)

And I'm getting this error:

Phase 1.1 Initial Placement Analysis
ERROR:Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
clkbuf1 of type BUFDS for the following reason.
The reason for this issue:
All of the logic associated with this structure is locked and the relative
placement of the logic violates the structure. The problem was found between
the relative placement of BUFDS clkbuf1 at site IBUFDS_GTXE1_X0Y0 and IPAD
SYSCLK_P at site IOB_X2Y119. The following components are part of this
structure:
BUFDS clkbuf1
IPAD SYSCLK_P

ERROR:Place:1073 - Placer was unable to create RPM[BUFDS_RPMs] for the component
clkbuf1 of type BUFDS for the following reason.
The reason for this issue:
All of the logic associated with this structure is locked and the relative
placement of the logic violates the structure. The problem was found between
the relative placement of BUFDS clkbuf1 at site IBUFDS_GTXE1_X0Y0 and IPAD
SYSCLK_N at site IOB_X2Y118. The following components are part of this
structure:
BUFDS clkbuf1
IPAD SYSCLK_N

Phase 1.1 Initial Placement Analysis (Checksum:78c67708) REAL time: 47 secs

ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

 

Please let me know any suggestions,

Thanks

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Xilinx Employee
Xilinx Employee
167 Views
Registered: ‎03-30-2016

Re: IBUFDS error in Virtex 6 GTX

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Hello @daranda314 

I believe SYSCLK_P/N is a reference clock for your GTX.
Is my understanding correct ?


If this is the case, your design is not implementable. I can see that you are using a global clock pins for GTX REFCLK.
     J9 34 IO_L0P_GC_34
     H9 34 IO_L0N_GC_34

Since you are using GTX in QUAD116, you need to use GTX REFCLK pins.
Please try to use the following pin p/n pair instead.
     F6 116 MGTREFCLK1P_116
     F5 116 MGTREFCLK1N_116
     H6 116 MGTREFCLK0P_116
     H5 116 MGTREFCLK0N_116

Thanks & regards
Leo

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3 Replies
Highlighted
Xilinx Employee
Xilinx Employee
168 Views
Registered: ‎03-30-2016

Re: IBUFDS error in Virtex 6 GTX

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Hello @daranda314 

I believe SYSCLK_P/N is a reference clock for your GTX.
Is my understanding correct ?


If this is the case, your design is not implementable. I can see that you are using a global clock pins for GTX REFCLK.
     J9 34 IO_L0P_GC_34
     H9 34 IO_L0N_GC_34

Since you are using GTX in QUAD116, you need to use GTX REFCLK pins.
Please try to use the following pin p/n pair instead.
     F6 116 MGTREFCLK1P_116
     F5 116 MGTREFCLK1N_116
     H6 116 MGTREFCLK0P_116
     H5 116 MGTREFCLK0N_116

Thanks & regards
Leo

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Highlighted
Xilinx Employee
Xilinx Employee
166 Views
Registered: ‎03-30-2016

Re: IBUFDS error in Virtex 6 GTX

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Hello @daranda314 

See also the following page for pinout information of your device,
    https://www.xilinx.com/support/packagefiles/v6packages/6vlx240tff1156pkg.txt
    https://www.xilinx.com/support/package-pinout-files/virtex-6-pkgs.html

Thanks & regards
Leo

Highlighted
Visitor
Visitor
136 Views
Registered: ‎11-04-2019

Re: IBUFDS error in Virtex 6 GTX

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Yes. I added this line:

NET SYS_CLK_N LOC=F5;
NET SYS_CLK_P LOC=F6;

and at least I got no errors.

Thanks