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yhy.xilinx
Adventurer
Adventurer
1,252 Views
Registered: ‎06-20-2019

IBUFDSGTE output is not routed properly

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Hello,

I am using Ultrazed 7ev SOM with CC and I designed some kind of a video application that is fully functional in simulation. I am using internal clock sources to run it on hardware. Yet, I am having trouble. In my design, I have a MIG which is using the PL DDR clock which is 300MHz. I cannot use this clock also to be an input of a PLL, this is a rule for MIG design. Thus, I tried to add PS to my design and use its PL fabric clock. When I used that, I haven't seen any output on hardware and ILA was not being armed(this is an indicator that ILA is not getting the clock properly). To check whether clock was utilized over the design or not, I connected PS's PL fabric clock output to an input of an MMCM. I assigned its locked pin to a LED and I saw that it wasn't being locked. Since I couldn't use both PS's PL fabric clock and 300MHz PL clock, I tried to use refclk of a GTH bank. In order to assign, I utilized IBUFDSGTE. The design was synthesized properly and I was able to assign the MGT clock as I wanted. However, when the implementation is finished, I saw "implementation completed, failed nets" writing right above. When I checked from the schematic, I saw that the output of IBUFDSGTE was not routed and it is stated that "it is routable but routed". I added CLOCK_DEDICATED_ROUTE=BACKBONE/FALSE constraint to overcome that failed nets issue but it didn't work. As much as I know, GCLK pins does not generate clock as long as you do not connect oscillator to them, too(I have no external oscillator). At this point, I am totally desperate about usage of clock. I didn't get why PS output was impractical. I thought that there is problem in the board itself(it is the first time using it). I created a basic up counter project to check if it can operate any sequential logic. When I used the 300MHz PL clock which is actually meant to be an input of a MIG, my counter project operates on hardware properly. When I use the PS's PL fabric output clock it doesn't. Can you give a guidance about what might be happening or is there something that I do not know?

 

Thank you very much for your valuable time.

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karnanl
Xilinx Employee
Xilinx Employee
1,125 Views
Registered: ‎03-30-2016

Hello @yhy.xilinx 

Sorry for the confusion, @roym is correct please try using BUFG_GT instead.


Regards
Leo


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karnanl
Xilinx Employee
Xilinx Employee
1,218 Views
Registered: ‎03-30-2016

Hello @yhy.xilinx 

Pardon me, I am not sure if I can understand your problem correctly.
Are you trying to connect IBUFGDS_GTE output (O pin) to your fabric logic ?

If this is the case,
You need to connect IBUFGDS_GTE O pin signal into BUFG and use BUFG output signal to clock your logic. Something like this :
Please_add_BUFG.jpg
Clock from IBUFGDS_GTE O pin cannot be used in fabric directly.

Thanks & regards
Leo


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If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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yhy.xilinx
Adventurer
Adventurer
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Registered: ‎06-20-2019
Hello @karnanl,

Thank you very much for your answer. Yes, that is the case. However, I had already connected output of the IBUFGDS_GTE to an MMCM whose input is adjusted as GLOBAL BUFFER. I knew that it is not different than using external bufg and MMCM with No Buffer but I tried since you emphasized the importance of BUFG. However, it is still not being routed(still Failed Nets). Today, after trying for days, I decided to use the additional clock output signals of MIG(which worked) but I still do not get why I cannot use IBUFDSGTE or fabric clock output of PS.
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roym
Moderator
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1,174 Views
Registered: ‎07-30-2007

It is not completely clear to me from the title but if this is a US+ chip it would need a BUFG_GT instead of a normal BUFG.




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karnanl
Xilinx Employee
Xilinx Employee
1,126 Views
Registered: ‎03-30-2016

Hello @yhy.xilinx 

Sorry for the confusion, @roym is correct please try using BUFG_GT instead.


Regards
Leo


------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
Versal Example Designs : LINK
>>------------------------------------------------------------------------------------------------

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yhy.xilinx
Adventurer
Adventurer
1,091 Views
Registered: ‎06-20-2019

Hello @karnanl, hello @roym,

Thank you for your responses again. Sorry if it became confusing question.Indeed, I asked multiple questions and what you understood is definitely the main one. I tried to use a clock pin of a MGT bank to be utilized in another bank.I have tried what you said and replaced BUFG with BUFG_GT. However, the tool gave me this error:
[DRC REQP-1926] IBUFDS_GTE4_O_cant_drive_BUFG_GT: BUFG_GT IBUFDSGTE/util_ds_buf_1/U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U I pin cannot be driven by the O pin of an IBUFDS_GTE4 (IBUFDSGTE/util_ds_buf_0/U0/USE_IBUFDS_GTE4.GEN_IBUFDS_GTE4[0].IBUFDS_GTE4_I). The IBUFDS_GTE4 ODIV2 pin is able to reach the BUFG_GT. The O pin of the IBUFDS_GTE4 may only be connected to the GTREFCLK pins of a GTHE4_COMMON, GTHE4_CHANNEL, GTYE4_COMMON, or GTYE4_CHANNEL component.

The implementation was not completed that time. It failed during place and route stage. I wanted to add GTHE_COMMON/CHANNEL... as it is suggested with error. The document UG974 states that normally one shouldn't use them. They cannot be instantiated or inferred.

However, after I connected IBUFDS_GTE4 ODIV2 output instead of IBUFDS_GTE4_O, it worked.

 

Thank you for your answers again.

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