cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Explorer
Explorer
469 Views
Registered: ‎12-05-2016

IO standard of GTX transceivers

Jump to solution

Hi all,

I am planning to test the GTX transceivers available on my custom board. Device is XC7K325TFBG676.  We are using MGT_BANK_115.  I just tried to write a simple parallel to serial program for sending data through this lines. But i couldnt place the corresponding I/O pins. But the pins are automatically placed if I am implementing an IBERT core. Why it is like that? What is the IO standard of transceiver pins? I am totally a newbie to this area. Any help is appreciated. 

Thanks & Regards,

Reshma  

0 Kudos
1 Solution

Accepted Solutions
Highlighted
456 Views
Registered: ‎01-08-2012

Re: IO standard of GTX transceivers

Jump to solution

The transceiver I/Os are not regular SelectIO I/Os in the sense that they don't have a configurable IO Standard, and they cannot be routed to the regular logic in the FPGA.  They are permanently connected to the transceivers, and only the transceivers.

For your test design, you must get to those pins through the transceivers.  I suggest reading the relevant user guide (which I think is UG476 for the part you have).

View solution in original post

1 Reply
Highlighted
457 Views
Registered: ‎01-08-2012

Re: IO standard of GTX transceivers

Jump to solution

The transceiver I/Os are not regular SelectIO I/Os in the sense that they don't have a configurable IO Standard, and they cannot be routed to the regular logic in the FPGA.  They are permanently connected to the transceivers, and only the transceivers.

For your test design, you must get to those pins through the transceivers.  I suggest reading the relevant user guide (which I think is UG476 for the part you have).

View solution in original post