Solved: Implementation of USB PHY layer on GTH transceiver

verilog_bee · ‎03-22-2019

Greetings,

Hi, I am a new bee at Xilinx. I want to use Ultrascale GTH transceiver for my USB 3.1 gen1 gen2 IP. is it possible to implement USB PHY on a transceiver? And does Xilinx support its configuration preset like I have seen in GTH wizard for 1g_10_25g_switchable.

Is there any reference design available for USB PHY on GTH transceiver? please guide us.

csattar · ‎03-23-2019

hi @verilog_bee ,

unfortunately, xilinx offically do not support the USB , hence there is no USB IP from xilinx .

Regards
Chandra sekhar
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csattar · ‎03-23-2019

hi @verilog_bee ,

unfortunately, xilinx offically do not support the USB , hence there is no USB IP from xilinx .

Regards
Chandra sekhar
----------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if solution provided is helpful.

Give Kudos to a post which you think is helpful and reply oriented.
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View solution in original post

Implementation of USB PHY layer on GTH transceiver

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Re: Implementation of USB PHY layer on GTH transceiver