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Visitor dmtutd
Registered: ‎02-08-2018

Incorrect assignment for RXUSRCLK when using multiple GT channels

I used the 7 Series GTX Wizard to create a design that uses two GT channels in my GTX Quad. Both GT channels only use the RX side (TX turned off). One RX channel is a 1.485 Gbps interface while the other is a 2.97 Gbps interface (ie. one will have a 74.25 MHz recovered clock while the other will have a 148.5 MHz recovered clock). When I ran my simulation, I found that both the GT0_RXUSRCLK and G1_RXUSRCLK are the same, so I tracked down the code and found that the GT0_RXUSRCLK_OUT and GT1_RXUSRCLK_OUT outputs (in XXX_usrclk_source.vhd) are both being assigned to gt0_rxusrclk which is the recovered clock from the GT0 channel.


I saw another post regarding the TXOUTCLK having the same issue, but since this is on the RX side, it seems odd that they would do this since I would assume that most applications would use the recovered clock from its appropriate channel.


Is this a bug or is this just standard operating procedure for the wizard and it's up to the user to modify this file?




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Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007

回复: Incorrect assignment for RXUSRCLK when using multiple GT channels

hi @dmtutd


You may have to generate two GT Channels wrapper with GTX Wizard. It cannot generate the two line rates GT channels at a time.


Please select Shared Logic In "example Design". So the GT common will be placed in example design. You can connect one GT common to the two CT channels.




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