09-22-2017 02:40 AM
I'm relatively new to phase noise/jitter. In our prototype we're interested in using line rates of 6.6 Gbps and 12.5 Gbps. There are a variety of companies that offer clock synthesizer that we can use to generate a reference clock for our transceivers. When browsing through the possibilities, I'm faced with question of the "jitter integration bandwidth". For example, in the link below, this range is set by default: https://www.silabs.com/tools/Pages/phase-noise-jitter-calculator.aspx
Is this range specified by Xilinx for its transceivers? For example, Xilinx does specify the offset frequencies along with the phase noise: https://www.xilinx.com/support/answers/44549.html
What can directly influence this range?
Thanks in advance for your feedback.
09-22-2017 09:01 AM
we only specify the phase noise mask for the transceiver reference clock and not an integrated value.
Please choose a reference clock source that provides the phase noise information.
Otherwise you might choose a source that violates the mask and you might run into performance issues on your link.
09-29-2017 04:52 AM
Thanks for your reply.
As you've mentioned, we're following the recommendations with respect to phase noise/reference clock.
The lacking information is the jitter RMS value. In order to get this value, it must be either directly written in a Xilinx documentation or calculated based on other values provided by Xilinx (e.g. phase noise table in the link provided above).
Using an online calculator like the one provided by SiLabs requires one more input (in addition to the phase noise table) which is the "jitter integration bandwidth".
Another accepted answer will be to directly provide me with the jitter RMS value i.e. Should the jitter RMS value be:
# ~ 0.3 ps
# ~ 0.125 ps
# ~ 0.08 ps
Please keep in mind that the intended line rate will always be closer to the upper limit supported by XC7K160T-2FBG where all lanes will be used.