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Registered: ‎02-07-2020

Instantiating the IBERT 7 series GTX IP core

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I'm trying to set up the IBERT 7 Series GTX IP Core for part xc7k160tfbg676-2.  I've read through PG132 and still don't fully understand it and can't successfully instantiate it.

I want to test the interface over SMA cables on my board, so a TX output to an external pin and then an RX input from an external pin.  I have a 125 MHz oscillator tied to MGTREFCLK1P_116 and MGTREFCLK1N_116.  The below 3 images show how I configure the IP Core.  After configuring it, I created an example project based on it, the top level Verilog is also below.  The example project created IBUFDS_GTE2 primitives that take the differential 125 MHz GRREFCLK device inputs and output the single ended refclk that gets fed into the IP core GTREFCLK input.

When I try to generate the bitstream, I get an implementation error:

[DRC PDCN-2713] GTXE2_COMMON_valid_IBUFDS_GT_connection: GTXE2_COMMON u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common uses multiple REFCLK pins which prevents pin swapping and is driven by an IBUFDS_GTE2 u_buf_q0_clk0 which as placed does not connect to the chosen REFCLK pin u_ibert_core/inst/QUAD[0].u_q/u_common/u_gtxe2_common/GTREFCLK0. Either use a single REFCLK so pin swapping can select a valid pin, or change the IBUFDS_GTE2 placement, or use a REFCLK pin (GTREFCLK1) which matchs the IBUFDS_GTE2 placement.

This happens whether or not I feed a single refclk to both IP Core GTREFCLK inputs.  I'm using Vivado 2019.1.

What's happening here?  Is there another primitive or PLL the reference clocks need to be sent through in order to be inputted as GTREFCLKs in the IBERT core?

 

`define C_NUM_QUADS 1
`define C_REFCLKS_USED 1
module example_ibert_7series_gtx_0
(
  // GT top level ports
  output [(4*`C_NUM_QUADS)-1:0]		TXN_O,
  output [(4*`C_NUM_QUADS)-1:0]		TXP_O,
  input  [(4*`C_NUM_QUADS)-1:0]    	RXN_I,
  input  [(4*`C_NUM_QUADS)-1:0]   	RXP_I,
  input  [`C_REFCLKS_USED-1:0]        	GTREFCLK0P_I,
  input  [`C_REFCLKS_USED-1:0]        	GTREFCLK0N_I,
  input  [`C_REFCLKS_USED-1:0]        	GTREFCLK1P_I,
  input  [`C_REFCLKS_USED-1:0]        	GTREFCLK1N_I
);

  //
  // Ibert refclk internal signals
  //
  wire   [`C_NUM_QUADS-1:0]        	gtrefclk0_i;
  wire   [`C_NUM_QUADS-1:0]        	gtrefclk1_i;
  wire   [`C_REFCLKS_USED-1:0]        	refclk0_i;
  wire   [`C_REFCLKS_USED-1:0]        	refclk1_i;

  //
  // Refclk IBUFDS instantiations
  //

    IBUFDS_GTE2 u_buf_q0_clk0
      (
        .O            (refclk0_i[0]),
        .ODIV2        (),
        .CEB          (1'b0),
        .I            (GTREFCLK0P_I[0]),
        .IB           (GTREFCLK0N_I[0])
      );

    IBUFDS_GTE2 u_buf_q0_clk1
      (
        .O            (refclk1_i[0]),
        .ODIV2        (),
        .CEB          (1'b0),
        .I            (GTREFCLK1P_I[0]),
        .IB           (GTREFCLK1N_I[0])
      );

  //
  // Refclk connection from each IBUFDS to respective quads depending on the source selected in gui
  //
  assign gtrefclk0_i[0] = refclk0_i[0];
  assign gtrefclk1_i[0] = refclk1_i[0];
// // IBERT core instantiation // ibert_7series_gtx_0 u_ibert_core ( .TXN_O(TXN_O), .TXP_O(TXP_O), .RXN_I(RXN_I), .RXP_I(RXP_I), .GTREFCLK0_I(gtrefclk0_i), .GTREFCLK1_I(gtrefclk1_i) ); endmodule

bert1.pngbert2.pngbert3.png

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Registered: ‎02-07-2020

Re: Instantiating the IBERT 7 series GTX IP core

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That Verilog file was the output of the Example Design. I eventually figured out the issue. Once you instantiate the IBERT with a given GTX location and pins, you can't change it. If I try to reinstantiate or edit it with new pins, it won't work. I need to delete the IP core and start again.

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Registered: ‎07-30-2007

Re: Instantiating the IBERT 7 series GTX IP core

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You don't instantiate the IBERT like that.  You open the example design for the settings you show and then implement it.  IBERT is standalone it can't be integrated into another design.  In Vivado right click on the IBERT instance and "open example design" should be one of your choices.




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Highlighted
117 Views
Registered: ‎02-07-2020

Re: Instantiating the IBERT 7 series GTX IP core

Jump to solution
That Verilog file was the output of the Example Design. I eventually figured out the issue. Once you instantiate the IBERT with a given GTX location and pins, you can't change it. If I try to reinstantiate or edit it with new pins, it won't work. I need to delete the IP core and start again.

View solution in original post