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Hrishikesh
Adventurer
Adventurer
627 Views
Registered: ‎09-26-2020

Integrated Interlaken LoopBack Test

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Hello,

I want to do loopback test of Integrated interlaken block in our 19eg custom board.

There is no reference on how to test the example design for Integrted Interlaken block, Can someone help in testing this block.

I am using Integrated Interlaken block 1 of 19EG, with 12 lanes of GTH transceivers with 12.5GBps line rate. FMC loopback card is used for loopback of the transceivers.

Thanks in Advance

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yannickl
Xilinx Employee
Xilinx Employee
569 Views
Registered: ‎11-03-2016

Hi,

Chapter 5 of pg169 v2.4 describe exactly steps required to use and test the example design. You should check table 5-2 of page 112 which describes the important signals.

pg169-interlaken.pdf 

Regards,

YL

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yannickl
Xilinx Employee
Xilinx Employee
570 Views
Registered: ‎11-03-2016

Hi,

Chapter 5 of pg169 v2.4 describe exactly steps required to use and test the example design. You should check table 5-2 of page 112 which describes the important signals.

pg169-interlaken.pdf 

Regards,

YL

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Hrishikesh
Adventurer
Adventurer
514 Views
Registered: ‎09-26-2020

Hello,

I am not very clear with the documentation, whether that IP Example design is only meant for simulation purpose or can it also be used for testing on hardware ? If it can be used for testing with hardware then how does duplex loopback work whether its internal loopback or external loopback using FMC ? The document does not mention it anywhere. 

inter.png

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Hrishikesh
Adventurer
Adventurer
514 Views
Registered: ‎09-26-2020

Can we get access to the design demonstrated in this video https://www.xilinx.com/products/intellectual-property/interlaken.html ? If not are there any references to create a similar design. 

Thank you in Advance

jon510
Newbie
Newbie
344 Views
Registered: ‎03-19-2021

Hi Hrishikesh,

Have you found something about the design shown in the video? I'm also interested to get access to it.

Thanks!

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Hrishikesh
Adventurer
Adventurer
328 Views
Registered: ‎09-26-2020

Hello,

No we did not get access to it.

We can just use the Interlaken example design.

While using the example design to prove using two boards certain sequence must be followed.

First thing is you need to add a vio to ctl_tx_enable signal in the example design top module.

you need to run example designs on both boards, make ctl_tx_enable at the first board as high. check whether tx is done from that board and rx done at partner board.

next make ctl_tx_enable on second board as high.

by following this you can prove the example design.

jon510
Newbie
Newbie
295 Views
Registered: ‎03-19-2021

Hi Hrishikesh,

Thank you so much for your reply and advice. Those are very helpful.

We will use the example design, and make sure to follow your procedure.

Kind regards,

Jon

 

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