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Visitor
Visitor
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Registered: ‎10-24-2019

Interfacing UFS(M-phy) with FPGA

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Hi Team,

We have a requirement to interface FPGA(Ultrascale) with UFS memory(M-PHY Protocol) device. We do understand that neither Ultrascale nor Ultrascale + natively support M-Phy protocol. Therefore we are planning to design a signal conditioning circuit that would allow us to connect a UFS to  FPGA. 

 

UFS memory supports M-PHY Protocol and has Differential input/output voltage: 140mv to 250 mV(DIF_AC_LA_RT_TX ) and Common mode voltage of 160mV to 260 mV(VCM_LA_TX )

 

Below mentioned is the design plan to make the common-mode voltage(CM) and Peak to Peak voltage(VPP) compatible.

>Provide an AC coupling capacitor in series(typically M-PHY is DC coupled) and terminate both sides (FPGA and UFS) to the required common-mode voltage.

(FPGA TX and UFS RX)

Solution for VPP: Program the "TXDIFFCTRL[4:0]" to set the DVPPOUT to 223mV or 191mV( UFS supports:140mv to 250 mV(DIF_AC_LA_RT_TX )).

Solutions for CM: Terminate the UFS side with a voltage of 200mV(External termination)( UFS supports: 160mV to 260 mV(VCM_LA_TX )

(UFS TX and FPGA RX)

Solution for VPP: FPGA accepts DVPPIN 150mV to 1250mV. therefore no modification required.

Solution for CM: Configure the RX common-mode voltage"RX_CM_TRIM[3:0]" to 200mV.( UFS supports: 160mV to 260 mV(VCM_LA_TX )

 

May I request you to review this approach and let us know your thought on the same?

 

Regards,

Gireesh

 

 

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @gireesh.nair 

Let me share my understanding.

1. Currently Xilinx device IOs (both GT Transceivers, or Select IOs) do not support M-PHY.
    # Please check datasheet for each device

2. Perhaps support for HS-mode/gears is possible using your proposal,
    but I don't think Xilinx GT can support LS-mode (Sleep/PWM mode etc), the line-rate is too slow and electrical spec is not compatible.

Thanks & regards
Leo

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello @gireesh.nair 

Let me share my understanding.

1. Currently Xilinx device IOs (both GT Transceivers, or Select IOs) do not support M-PHY.
    # Please check datasheet for each device

2. Perhaps support for HS-mode/gears is possible using your proposal,
    but I don't think Xilinx GT can support LS-mode (Sleep/PWM mode etc), the line-rate is too slow and electrical spec is not compatible.

Thanks & regards
Leo

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Visitor
Visitor
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Registered: ‎02-20-2014

We are also interested in UFS flash.  Without a membership to MIPI even getting the basic specs is not possible.  Are the specs you mentioned publicly available?  I know this is much less desirable, but are there commercial transceivers that can be used outside of the FPGA?  I see that Silicon Motion has bridge controllers with a USB interface, but a direct FPGA connection is the goal.

Phil

 

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Visitor
Visitor
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Registered: ‎02-20-2014

Answering my own question, I found this Arasan IP for the M-PHY on Virtex 7 here: https://www.arasan.com/news/arasan-and-xilinx-announce-their-design-win-in-providing-a-total-ufs-3-0-solution-to-wuhan-jingce/ 

Will look into if it can be applied to Ultrascale+.