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Observer
Observer
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Registered: ‎09-21-2018

Interpretation of MGT Reference Clock Differential Input Voltage

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We are designing a board using the GTY/GTH transceivers a Zynq US+ MPSoC.  I am trying to determine the allowable differential input voltage range for the GTY/GTH reference clocks.  DS925 specifies differential input voltage VIDIFF as 250-2000mVpp in Table 109.  But if I believe Figure 6 on the same page, then this VIDIFF spec is actually 2x the differential voltage that would be measured between the MGTREFCLKP and MGTREFCLKN pins (i.e. absolute value | Vp - Vn | )?  Am I correct in this interpretation of the VIDIFF spec?  So the output differential voltage VOD from my clock driver must fall within 1/2 the VIDIFF range (i.e. 125 - 1000mV) to be compliant?

If the above is correct, I must ask why is the GTY Clock VIDIFF spec given this way? Elsewhere in the same datasheet, differential input voltage VIDIFF does not have the 2x factor.  For example, see DS925 Table 23 where LVDS_25 VIDIFF is just | Qp - Qn |, no 2x factor.

Thanks, Ted  

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Xilinx Employee
Xilinx Employee
632 Views
Registered: ‎08-25-2010

Hi @vttmw93,

 

It's correct, and there is a 2x factor as shown in figure 5 and figure 6. Figure 5 emphasize the single-end clock input(LVDS_P or LVDS_N)voltage swing(or peak-to-peak), more used to illustrate general SelectIO. Figure 6 illustates the differential clock input voltage swing, which is defined as MGTREFCLKP – MGTREFCLKN, used to GT transceiver clock.

Thanks
Simon
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Xilinx Employee
Xilinx Employee
633 Views
Registered: ‎08-25-2010

Hi @vttmw93,

 

It's correct, and there is a 2x factor as shown in figure 5 and figure 6. Figure 5 emphasize the single-end clock input(LVDS_P or LVDS_N)voltage swing(or peak-to-peak), more used to illustrate general SelectIO. Figure 6 illustates the differential clock input voltage swing, which is defined as MGTREFCLKP – MGTREFCLKN, used to GT transceiver clock.

Thanks
Simon
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Observer
Observer
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Registered: ‎09-21-2018

Thanks Simon.

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