04-16-2018 02:48 AM
I have a design to support multi-rate change by using the GTX in KC705, the connection is as below:
KC705's GTX <-> USER PCS <-> USER MAC
The design must support the speed rate change 10.3125G/3.125G/1.25Gbps in one bit file, following is related info:
GTX general setting: only use the PMA part, bypass the PCS and disable Tx/Rx gearbox
In 10.3125Gbps mode:
USER PCS data width is 32bits, and need the TX/RXCDRCLK 322.265625MHz and 156.25MHz from GTX.
I using TX/RXOUTCLK 322.265625MHz feeded into MMCM to generate TX/RXCDRCLK 156.25MHz.
In 3.125G/1.25Gbps mode:
USER PCS data width is 10bits, and need the TX/RXCDRCLK 312.5MHz/125MHz(3.125G/1.25G) from GTX.
1) Data Width: the GTX setting seems only support 20bits minimum width with CLK 156.25MHz/62.5MHz(3.125G/1.25G),
so I implement the bridge design to transfer the width from 20bits to 10bits.
2) CLK: I using TX/RXOUTCLK 156.25MHz/62.5MHz(3.125G/1.25G) feeded into MMCM to generate TX/RXCDRCLK 312.5MHz/125MHz(3.125G/1.25G).
- Is there any another programmable CLK form GTX for my USER PCS usage?
- For 3.125G/1.25G mode, data width limitation, is it possible to set 10bits witdh?
04-16-2018 05:56 AM
Are you using the DRP to reconfigure GTX in your design for the different data rates? If so, it looks like you can change the MMCM configuration through its DRP as well.
Check this out and see if it will work for you.
04-16-2018 08:21 AM
I believe this can be done. I have successfully implemented designs that supported multiple data rates in the past. I have had the most success with instantiating the GTX primitives directly instead of trying to use the Wizard to generate something. In answer to your questions, though:
- The minimum width of the GTX is 16 bits (20 bits if using 8b/10b), so you will need to do some sort of external gearbox/bridge to get down to 10 bits.
- RXOUTCLK is the one you want to use for your RX datapath. On the TX datapath, if you happen to have another clock that is synchronous to your reference clock, you could use that if you wanted to...
04-16-2018 08:45 AM
Actually, the method I mentioned is works fine. And for the multi-rate settings, I also using the DRP to configure the different rate.
I just like to know if there are another method to not using additional MMCM to generates these two CDR clock that I needed.
For example, I know the GTY(ultrascale plus) architecture have another programmable CDR clock output, so it can provide 322.265625MHz and 156.25MHz CDRCLK at the same time. (But now, I only have KC705 device)
Because these multi-rate clock architecture using so many MMCM and BUFG. I would like to saving more BUFG for another clock design purpose.
04-16-2018 09:44 AM
I guess you are referring to the UltraScale GT RX PROGDIV path and the BUFGCE_DIV primitive. These new features make the UltraScale FPGA clock tree more flexible and help to save MMCMs/BUFG.
04-16-2018 10:05 AM
What is the frequency of the GTX reference clock?
Take a look at TX Fabric Clock Output Control, figure 3-28 and RX Fabric Clock Output control, figure 4-23 to see if by changing TXOUTCLKSEL/RXOUTCLKSEL ports from a register, you can get the frequency you are looking for. Failing this, I don't see any way to do what you want in the 7Series tranceivers.