ADS54J66
JESD RX - Line rate = 6.238Gbps, LMFS = 4421, K = 32, RefClk = 155.968MHz, CoreClk = 155.968MHz, Sysref always ON, Sysref = 2.437MHz
Subclass 1
This configuration works when the ADC is connected to HPC1 but it fails when connected to HPC0.
rx_sync toggles continuously after triggering sysref and there are disparity and not in table errors.
ADC connected to HPC0 rx_sync toggles after triggering sysref
I have tried inverting rx lanes polarity by writing 1 to gt_rxpolarity and changing sysref frequency but none of this helped. I would appreciate your helpful guidance in debugging this issue.
The AXI registers are
rd_rx00 07020400
rd_rx04 00000000
rd_rx08 00000001
rd_rx0C 00000000
rd_rx10 00000001
rd_rx18 00000000
rd_rx1C 00000fff
rd_rx20 00000001
rd_rx24 0000001f
rd_rx28 0000000f
rd_rx2C 00000001
rd_rx30 00000000
rd_rx34 00000001
rd_rx38 00010000
rd_rx3C 0000cfff
Lane 0
rd_rx800 00000505
rd_rx804 000000bc
rd_rx808 0000001c
rd_rx80C 1c0802c9
rd_rx810 021c1cbc
rd_rx814 1c011c00
rd_rx818 00bcbc9c
rd_rx81C 00000002
rd_rx820 00000000
rd_rx824 35f61c1e
rd_rx828 00000000
rd_rx82C 00000000
rd_rx830 00000000
Lane 1
rd_rx840 00000303
rd_rx844 0000003c
rd_rx848 00000015
rd_rx84C 160100b2
rd_rx850 001a153c
rd_rx854 03011100
rd_rx858 002665ca
rd_rx85C 0001010d
rd_rx860 00000000
rd_rx864 3876c5c4
rd_rx868 00000000
rd_rx86C 00000000
rd_rx870 00000000
Lane 2
rd_rx880 00000505
rd_rx884 000000bc
rd_rx888 0000001c
rd_rx88C 1c1c0cbc
rd_rx890 021c1cbc
rd_rx894 1c011c01
rd_rx898 00bcbc9c
rd_rx89C 0000010b
rd_rx8A0 00000000
rd_rx8A4 3b7e92bf
rd_rx8A8 00000000
rd_rx8AC 00000000
rd_rx8B0 00000000
Lane 3
rd_rx8C0 00000304
rd_rx8C4 000000ad
rd_rx8C8 0000000e
rd_rx8CC 12090a12
rd_rx8D0 031d1bd0
rd_rx8D4 13001f01
rd_rx8D8 000f0f7b
rd_rx8D8 00000108
rd_rx8E0 00000000
rd_rx8E4 ffffffff
rd_rx8E8 00000000
rd_rx8EC 00000000
rd_rx8F0 00000000
OUTPUT when ADC connected to HPC1
ADC connected to HPC1
Pin mapping
ADC connected to HPC1
set_property -dict {PACKAGE_PIN G27} [get_ports rxrefclk_p]
set_property -dict {PACKAGE_PIN G28} [get_ports rxrefclk_n]
set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVDS} [get_ports rxglblclk_p]
set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVDS} [get_ports rxglblclk_n]
set_property -dict {PACKAGE_PIN AH1 IOSTANDARD DIFF_HSTL_I_18} [get_ports rx_sysrefp]
set_property PACKAGE_PIN B33 [get_ports {rxp_in[0]}]
set_property PACKAGE_PIN C31 [get_ports {rxp_in[1]}]
set_property PACKAGE_PIN D33 [get_ports {rxp_in[2]}]
set_property PACKAGE_PIN E31 [get_ports {rxp_in[3]}]
set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVDS} [get_ports rx_syncp]
set_property -dict {PACKAGE_PIN T13 IOSTANDARD LVDS} [get_ports rx_alt_syncp]
ADC connected to HPC0
set_property -dict {PACKAGE_PIN G8} [get_ports rxrefclk_p]
set_property -dict {PACKAGE_PIN G7} [get_ports rxrefclk_n]
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVDS} [get_ports rxglblclk_p]
set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVDS} [get_ports rxglblclk_n]
set_property -dict {PACKAGE_PIN Y2 IOSTANDARD DIFF_HSTL_I_18} [get_ports rx_sysrefp]
set_property PACKAGE_PIN K2 [get_ports {rxp_in[0]}]
set_property PACKAGE_PIN F2 [get_ports {rxp_in[1]}]
set_property PACKAGE_PIN J4 [get_ports {rxp_in[2]}]
set_property PACKAGE_PIN H2 [get_ports {rxp_in[3]}]
set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVDS} [get_ports rx_syncp]
set_property -dict {PACKAGE_PIN T7 IOSTANDARD LVDS} [get_ports rx_alt_syncp]
@nathanx @roym @barriet
1 Solution
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