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raj
Adventurer
Adventurer
1,039 Views
Registered: ‎05-24-2020

JESD204 GTH transceiver location on ZCU102

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I have JESD RX and TX as below - 

ADS54J66
JESD RX -  Line rate = 6.546Gbps, LMFS = 4421, RefClk = 163.654MHz, CoreClk = 163.654MHz, Sysref always ON

DAC37J82
JESD TX -  Line rate = 8.1088Gbps, LMFS = 4211, RefClk = 202.72MHz, CoreClk = 202.72MHz, Sysref always ON

RefClk to RX and TX are coming from two separate LMK04828 IC. 

I am designing a custom analog board that has ADC and DAC on it to interface with ZCU102 and I am looking for guidelines on GTH transceiver location and choice of connector (HPC0 or HPC1). Can I connect both ADC and DAC to the same connector (HPC0 or HPC1) or do they have to be connected to different connectors given the line rates and RefClks are not same? 

Can I have one JESD PHY that connects to both RX and TX ? Or two different JESD PHY ?

Alternately, can JESD TX and RX be placed in adjacent GTH banks since the line rates are different ? I referred to Figure 3-36 of UG1182, PG198 and PG066 but it's not clear what the requirements are for GTH location based on the RX and TX line rate. 

Could you please recommend a configuration for this JESD RX and TX setup. Number of JESD PHY, transceiver location and PCB design guidelines to ensure good signal integrity.  Thank you

ZCU102 GTH bank assignmentZCU102 GTH bank assignment

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barriet
Xilinx Employee
Xilinx Employee
939 Views
Registered: ‎08-13-2007

Are you using a purchased/full IP license for the JESD204 core or the evaluation license? The latter has a synthesized timeout that will quit working in 2-8 hours (depending on core, configuration, clock, etc.)... That might not be your issue but given the apparent repeatability here - wanted to make sure that wasn't the issue.

https://www.xilinx.com/products/intellectual-property/ip-evaluation.html

I've seen that on a few other cores where the user forgot this and it complicated the hardware debug process. e.g. "it was working when I left the lab last night - this morning it isn't - and it works again as soon as I reload the bitstream."

Cheers,

bt

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6 Replies
roym
Moderator
Moderator
973 Views
Registered: ‎07-30-2007

It seems you want to provide your own reference clocks.  I would say if your ok using an FMC connector for this 228 and 229 are a good choice.  I think I would keep TX and RX in separate quads if they use different reference clocks.  That way you won't need to make changes to the wizard design.  They don't absolutely have to be in separate quads but it would be easier since they are running different line rates.




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raj
Adventurer
Adventurer
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Registered: ‎05-24-2020

@roym @karnanl 

Thank you for your recommendation. I am trying to test the stability of JESD link on HPC0 and HPC1 connectors of ZCU102 board. So far, I have tested it in two configurations -

1) Texas Instruments ADC ADS54J66EVM evaluation board connected to HPC1 or HPC0. (Subclass 1)

2) External FMC loopback on HPC1 using XM107. RefClk sourced from U56 Si570. (Subclass 0)

I have detailed my experience in my post here https://forums.xilinx.com/t5/Xilinx-IP-Catalog/JESD-loses-sync/m-p/1126693


ZCU102 external loopback using XM107ZCU102 external loopback using XM107
In both these tests, the RX link is in sync for approx. between 2hr5mins to 2hr20mins. It has never been stable and in sync for more than 2.5hrs. In my application I am expecting the link to be stable for over 24hrs. 

Could you please suggest guidelines on debugging this. I want to understand ZCU102 board's behavior for JESD links before designing a custom analog board that connects to ZCU102 via HPC0 and HPC1. Thank you

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barriet
Xilinx Employee
Xilinx Employee
940 Views
Registered: ‎08-13-2007

Are you using a purchased/full IP license for the JESD204 core or the evaluation license? The latter has a synthesized timeout that will quit working in 2-8 hours (depending on core, configuration, clock, etc.)... That might not be your issue but given the apparent repeatability here - wanted to make sure that wasn't the issue.

https://www.xilinx.com/products/intellectual-property/ip-evaluation.html

I've seen that on a few other cores where the user forgot this and it complicated the hardware debug process. e.g. "it was working when I left the lab last night - this morning it isn't - and it works again as soon as I reload the bitstream."

Cheers,

bt

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raj
Adventurer
Adventurer
896 Views
Registered: ‎05-24-2020

@barriet 

Thank you for your response. I was using a Hardware Evaluation license and that was the reason for rx_sync going low. I have purchased a license and it has solved my problem. Thank you 

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barriet
Xilinx Employee
Xilinx Employee
894 Views
Registered: ‎08-13-2007

@raj

Thank you for the update - I'm glad to hear that the issue was resolved... I wasn't sure that was the issue initially but wanted to make sure we considered that as an option here because it is an easy thing to overlook unfortunately.

Good luck with your design.

Cheers,

bt

raj
Adventurer
Adventurer
888 Views
Registered: ‎05-24-2020

@barriet 
As you mentioned, "it was working before I left and today it doesn't work" led me into this never ending, time consuming troubleshooting process. It is good to know evaluation licenses are not true "full" versions. Your colleague @roym provided a lot of detailed explanation and guidelines on resolving this issue, had it not been for a license. Thank you

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