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Adventurer
Adventurer
629 Views
Registered: ‎06-25-2012

JESD204-PHY with asymmetric TX / RX lane count

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In our application we need 10 lanes for Rx (ADC) and 8 lanes for Tx (DAC).

Our transceiver mapping is as follows:

X0Y6    225    X0Y1    ADC0    N/A
X0Y7    225    X0Y1    ADC1    N/A
X0Y8    226    X0Y2    ADC2    DAC0
X0Y9    226    X0Y2    ADC3    DAC1
X0Y10    226    X0Y2    ADC4    DAC2
X0Y11    226    X0Y2    ADC5    DAC3
X0Y12    227    X0Y3    ADC6    DAC4
X0Y13    227    X0Y3    ADC7    DAC5
X0Y14    227    X0Y3    ADC8    DAC6
X0Y15    227    X0Y3    ADC9    DAC7

 

What is the appropriate way to combine JESD204 PHY and JESD204 cores in order to utilize these lanes?

  • 1 JESD PHY, L = 10, connect all gt_rx outputs, connect gt_tx inputs 2-9, leave gt_tx input 0-1 as NC. Split RX lanes to 2 JESD204 cores with 6/4 RX inputs.
  • 2 JESD PHY, one with L=8 (use all GT inputs and outputs), one with L=2 (use only GT RX outputs). Split RX lanes to 2 JESD204 cores with 8/2 RX inputs.
  • Something else?

 

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Adventurer
Adventurer
534 Views
Registered: ‎06-25-2012

Re: JESD204-PHY with asymmetric TX / RX lane count

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To answer my own question, I have used 2 JESD PHY and 3 JESD core IP.

1 JESD PHY has 8x TX/RX connections (w/ shared logic in core), fully connected with 2 JESD core IP (x8 width).

1 JESD PHY has 2x Rx connections to 1 JESD core IP (x2 width).

3 Replies
Xilinx Employee
Xilinx Employee
588 Views
Registered: ‎08-07-2007

回复: JESD204-PHY with asymmetric TX / RX lane count

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hi @jsmithsrc

 

I think that is more like JESD to JESD PHY connection question.

You can post it to 'Networking and Connectivity' board.

 

Thanks,

Boris

 

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Adventurer
Adventurer
535 Views
Registered: ‎06-25-2012

Re: JESD204-PHY with asymmetric TX / RX lane count

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To answer my own question, I have used 2 JESD PHY and 3 JESD core IP.

1 JESD PHY has 8x TX/RX connections (w/ shared logic in core), fully connected with 2 JESD core IP (x8 width).

1 JESD PHY has 2x Rx connections to 1 JESD core IP (x2 width).

Observer cgrant
Observer
118 Views
Registered: ‎04-07-2015

Re: JESD204-PHY with asymmetric TX / RX lane count

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@jsmithsrc What are the ADC and DAC devices you are using that work this way?

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