11-13-2019 03:19 PM
I'm using Vivado to build a 4-lane JESD204B receiver core with JESD204 v7.2 IP targetting Kintex Ultrascale family. The Kintex Ultrascale family has a Quad architecture for the SerDes lanes where 4 SerDes lanes along with their own individual CPLLs, 2 QPLLs and 2 MGTREFCLKs are clustered together to form a Quad.
When I physically assign the SerDes lanes so that the 4 would end up in the same Quad, as a test, Place and Route completed without any problem. But when the assignment uses 2 lanes in one Quad and another 2 lanes in another Quad, PAR encountered error. It seems the IP automation connects things, clockings/resets/controls/JESD204 logic ..., in a way that the 4 lanes are expected to be in the same Quad and can not spread out across more than 1 Quad.
My question is that is there a tool-driven way to make the 4-lane design using 2 Quads work? without a significant effort to manually restructure the initial generated design by IP generator meaning I have to look at the generated design and manually re-architect it.
I do have a prototype where the 4 SerDes lanes coming from an ADC, over the FMC connector, end up in 2 Quads. 2 lanes goes to one Quad and another 2-lane set ends up in a different Quad.
Thank you very much for the insights,
11-14-2019 03:49 AM
Hi email@example.com ,
the JESD core expects the lanes to be continuous. If you leave the JESD PHY outside the JESD core and generate a JESD PHY separately, you can with the JESD PHY configuration select the starting lane fore the core. This would take into account if the continuous lanes span over several quads.
If the lanes are not continuous, it might be better to have several JESD PHY cores or JESD cores and combine the data later.
11-20-2019 05:44 PM
In future update of the tool, do you know if there's a plan to remove same-Quad and sequential transceiver location allocation from withthin the Core automation flow to give users some flexibility?
11-21-2019 06:43 AM
Hi firstname.lastname@example.org ,
I am not aware that this will be updated in the future.
12-03-2019 10:47 AM
1. If we were to take the manual route of trying to make the 4-lane interface to work using lanes in 2 different Quads which is a significant effort, are you aware of any application notes or docs that would help give us some directions and ultimately speed up this effort? Thanks.
2. We've been working on a different alternative which is to build an 8-lane interface instead that utilizes 2 full Quads and IP automation doesn't have a problem with this. In this mode the AXI interface becomes 256-bit instead of 128-bit and the JESD mode is 8-2-2-4. We have 2 ADC channels with 16-bit samples. We're trying to figure out the samples alignment from within each 256-bit sample and the IP datasheet doesn't quite cover this. What's mentioned is below for 4-lane and 2-lane modes. Do you have any insight on what this would look like for 8-2-2-4 8-lane mode with 256-bit? Thanks.
12-18-2019 09:59 PM - edited 12-19-2019 08:22 PM
JESD204 is a high-speed serial interface for connecting data converters (ADCs and DACs) to logic devices. Revision B of the standard supports serial data rates up to 12.5 Gbps and ensures repeatable, deterministic latency on the JESD204 link PrepaidGiftBalance Mastercard