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Observer
Observer
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Registered: ‎02-26-2020

KCU105 QPLL Common_X0Y2 Not Locked

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Hi,

I was trying to get the provided IBERT over SFP to work, however I haven't had any luck. At first I thought it was a some configuration that I missed, like the jumpers not being set, but I realized that the QPLL_0 COMMON_X0Y2 is not being locked. What could be the reason of this and how can I get it to lock?

Capture.PNG

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Moderator
Moderator
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Registered: ‎07-30-2007

Open the XCI and examine the reference clock selections.  What I see in XTP346 is refclk1 on quad 227 set to drive the sfp lanes on quad 226.  To do this you must program the Si5328 to the 156.25 Mhz frequency. It doesn't default to a frequency.  I think it would be easier to change to use the default 156.25 that is on refclk0 of quad227 that won't need programming.  You can see it is working as it is driving the quad 227 and 228.  You'll notice the frequency is low on 227 and 228 because the Si570 is at the default 156.25 and hasn't been programmed to the 163 Mhz that the IBERT expects.

You might find the vivado version of the design easier to work with in rdf0312 here:

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0034-ultrascale-hub.html

The better way to become familiar with your board is to go through XTP352 on the board set up (with emphasis on the clock set) up and get the SI5328 on 227 set to 156.25 Mhz. The tutorial will set all the clocks as needed for this tutorial. https://www.xilinx.com/support/documentation/boards_and_kits/kcu105/2017_3/xtp352-kcu105-setup-c-2017-3.pdf




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Moderator
Moderator
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Registered: ‎07-30-2007

Most often this is due to either no refclk or an unstable reference clock when the IBERT is configured.  That is the only time the QPLL is locked.  On bank 117 the sgmii clock (page 9 of the Ver 1.0 Rev 1 schematics)  which I believe is 125 Mhz is always there and would be the best to use. 

You can click on an MGT common and go to properties and search for the qpll*pd and/or the qpll*reset and manually toggle them to see it you can get it to lock. 

 




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Observer
Observer
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Registered: ‎02-26-2020

Hi,

I am running the "ibert_sfp.tcl" from the XTP346 so I assumed that the reference clocks and other settings are done in the tcl file. The other tests run fine except for the sfp one. Do you believe there is a problem with "COMMON_X0Y2" ? Should I try a 10G Ethernet Subsystem example design to verify the SFP Interfaces?

I tried toggling the qpll*pd and/or the qpll*reset and that didn't get it to lock.

Capture.PNG

 

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Moderator
Moderator
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Registered: ‎07-30-2007

Open the XCI and examine the reference clock selections.  What I see in XTP346 is refclk1 on quad 227 set to drive the sfp lanes on quad 226.  To do this you must program the Si5328 to the 156.25 Mhz frequency. It doesn't default to a frequency.  I think it would be easier to change to use the default 156.25 that is on refclk0 of quad227 that won't need programming.  You can see it is working as it is driving the quad 227 and 228.  You'll notice the frequency is low on 227 and 228 because the Si570 is at the default 156.25 and hasn't been programmed to the 163 Mhz that the IBERT expects.

You might find the vivado version of the design easier to work with in rdf0312 here:

https://www.xilinx.com/support/documentation-navigation/design-hubs/dh0034-ultrascale-hub.html

The better way to become familiar with your board is to go through XTP352 on the board set up (with emphasis on the clock set) up and get the SI5328 on 227 set to 156.25 Mhz. The tutorial will set all the clocks as needed for this tutorial. https://www.xilinx.com/support/documentation/boards_and_kits/kcu105/2017_3/xtp352-kcu105-setup-c-2017-3.pdf




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Observer
Observer
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Registered: ‎02-26-2020

Hi,

Yes, I did like you said and after programming the Si570 following XTP352 got the "ibert_sfp.tcl" working !!

One last question, does the Si570 needs to be reprogrammed every time that I power cycle ?

Thanks,

 

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Moderator
Moderator
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Registered: ‎07-30-2007

The SI570 will default to 156.25 on power up and can be reprogrammed to something else.  It should also be possible to reprogram the default power on frequency.  I have never tried this on this board but the save frequency to EEPROM looks like the right option.  I'm afraid you'll just have to try it.




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