cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
424 Views
Registered: ‎02-26-2020

KCU105 SFP+ IBERT Test Failure

Jump to solution

Hi,

I am trying to run a sanity check on the SFP+ with the example design provided on the rdf0312-kcu105-gth-ibert-c-2017-3.zip (XTP345), but it keeps failing.

I verified the connections and the cable and everything seems fine. 

I am specifically running the "ibert_sfp.tcl".

Here is a screenshot of the results:

Capture.PNG

 

 

 

Tags (3)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
Observer
Observer
247 Views
Registered: ‎02-26-2020

The issue was that the clock Si570 was not programmed so I had to program it to output the 163MHz required for this test.

See solution in this thread:

https://forums.xilinx.com/t5/Serial-Transceivers/KCU105-QPLL-Common-X0Y2-Not-Locked/m-p/1120817#M8188 

 

Thanks

View solution in original post

0 Kudos
5 Replies
Highlighted
Moderator
Moderator
345 Views
Registered: ‎07-30-2007

There is an enable for the SFP on that board.  TX disable on page 22 of the schematic.  Make sure it is on -Y20 on page 3 of the schematic.




----------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution
----------------------------------------------------------------------------


0 Kudos
Highlighted
Observer
Observer
325 Views
Registered: ‎02-26-2020

Hi,

There is no "TX_DISABLE" on page 22 nor Y20 on page 3, however I verified that the SFPs were enabled and according to the schematic this is done by simply having the jumpers on J6 and J7 (As described in XTP352 Pg 10) . These are in pages 27 and 28 of the schematic.

Capture.PNG

 

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
287 Views
Registered: ‎10-19-2011

Hi @oscar717 ,

did you setup the reference clock correctly? Your PLLs are not locked from the picture.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Highlighted
Observer
Observer
271 Views
Registered: ‎02-26-2020

Hi,

I am running the "ibert_sfp.tcl" file provided in the set of IBERT tests in XTP346 so I assumed that all reference clocks were set up correctly.

The other IBERT tests run successfully, it is only this ibert_sfp test that keeps failing.

Yes, COMMON_X0Y2 does not lock, but I don't know why. I tried the following tcl commands but that did not get the X0Y2 to lock:

set_property PORT.QPLL0RESET 1 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ]
set_property PORT.QPLL0RESET 0 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ]
set_property PORT.QPLL1RESET 1 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ]
set_property PORT.QPLL1RESET 0 [get_hw_sio_commons *];commit_hw_sio [list [get_hw_sio_commons {*}] ]
refresh_hw_sio [get_hw_sio_gts *]
refresh_hw_sio [get_hw_sio_commons *]

 

 

0 Kudos
Highlighted
Observer
Observer
248 Views
Registered: ‎02-26-2020

The issue was that the clock Si570 was not programmed so I had to program it to output the 163MHz required for this test.

See solution in this thread:

https://forums.xilinx.com/t5/Serial-Transceivers/KCU105-QPLL-Common-X0Y2-Not-Locked/m-p/1120817#M8188 

 

Thanks

View solution in original post

0 Kudos