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KCU116 GTY example design at 28G

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Visitor
Posts: 4
Registered: ‎05-18-2018

KCU116 GTY example design at 28G

Hello,

 

I am testing the example design of the GTY transceivers at the kcu116. I run loopback at the SFP transceiver and use the QPLL0 refclk (the jitter attenuator clk) and the 90 MHz sysclk for the free running clock. The thing is that it works fine up to 26 G but with the same settings I always receive errors on the receiver side when running at 28.125 G. Any suggestions?

 

Regards, Kosmas 

Moderator
Posts: 144
Registered: ‎05-02-2017

Re: KCU116 GTY example design at 28G

 

hi @kossad,

 

The GTY transceivers in the UltraScale architecture are power-efficient transceivers, supporting line rates from 500 Mb/s to 30.5 Gb/s in UltraScale FPGAs and 32.75 Gb/s in UltraScale+ FPGAs. The GTY transceiver is highly configurable and tightly integrated with the programmable logic resources of the UltraScale architecture.

 

What are errors your seeing and can you share your XCI file .

 

Chandra 

Visitor
Posts: 4
Registered: ‎05-18-2018

Re: KCU116 GTY example design at 28G

@csattar

 

I dont see any error or critical warning while generating the bitstream. The problem is that the "link_down_latched_out" signal always get 1 after reseting it.  The "link_status_out" stays high though as it should be. I am sharing the XCI file.

 

Kosmas