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rohithsaradhy
Observer
Observer
1,067 Views
Registered: ‎05-11-2018

Kintex 7 CPLL Lock done port

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Is there a port that can be used to know whether the CPLL recovered the clock from the rx correctly, meaning the rxoutclk is phase locked with the received data stream(I am sending in a clock into the Rx(of the sfp) for testing purposes.)

 

CPLLLOCK check only for the frequency and is not checking whether it is locking to the phase

 

Thanks,

Rohith.

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roym
Moderator
Moderator
1,057 Views
Registered: ‎07-30-2007

The RXCDRLOCK port helps with that but it is not entirely reliable.  The best method is to check the data.  If you have an 8B10B data stream just make sure you have no disparity or not in table errors.  If it is 64B/66B data then you would make sure the packet headers are being seen reliably.  Sending a clock is not the normal use case but I guess you could just make sure you see all 5555 or AAAA at the RX data port.

 

If you are sending from another Xilinx chip you could just send a PRBS pattern and use the PRBS checker.




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2 Replies
roym
Moderator
Moderator
1,058 Views
Registered: ‎07-30-2007

The RXCDRLOCK port helps with that but it is not entirely reliable.  The best method is to check the data.  If you have an 8B10B data stream just make sure you have no disparity or not in table errors.  If it is 64B/66B data then you would make sure the packet headers are being seen reliably.  Sending a clock is not the normal use case but I guess you could just make sure you see all 5555 or AAAA at the RX data port.

 

If you are sending from another Xilinx chip you could just send a PRBS pattern and use the PRBS checker.




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borisq
Xilinx Employee
Xilinx Employee
988 Views
Registered: ‎08-07-2007

hi @rohithsaradhy

 

besides methods that @roym  has mentioned, you can also take a look at this method.

https://www.xilinx.com/support/answers/66699.html

 

You can choose a best methods out of those.

 

Thanks,

Boris

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