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nipunnaina
Observer
Observer
1,692 Views
Registered: ‎08-29-2017

Kintex 7 GTX DRP ports example code required

Hello,

 

I want to run time data-rate change for kintex7 gtx.

In past, I have used the example codes from xilinx for DRP functions for PLL and MMCM. These were simple verilog files.

 

I am unable to find any example DRP code for GTX reconfiguration. If it is available please provide the same. A verilog file will be preferred.

 

 

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4 Replies
amaccre
Moderator
Moderator
1,606 Views
Registered: ‎04-24-2013

HI @soulefmassoud,

 

Judging from the error message that you received, I'm guessing that you are targeting a 7Series device.

 

In 7Series, clocks and clock modifying logic cannot be reconfigured as per UG909 and would be required to be in the static region of the deign.

 

Capture.PNG

 

Let me know if this helps.

 

Best Regards
Aidan

 

 

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nipunnaina
Observer
Observer
1,583 Views
Registered: ‎08-29-2017

 I wanted to change the line rate of GTX in kintex 7 FPGA using DRP reconfiguration. After lot of search I found 1 RTL file in VHDL for virtex 6 device. Please find the attachment.

 

As per my understanding xilinx would have already such files for reconfiguration using DRP for different devices.

I am not able to find the appropriate file for my device.

 

Can I get latest file verilog file for drp control for kintex 7 device?

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nipunnaina
Observer
Observer
1,549 Views
Registered: ‎08-29-2017

any updates for my query?

 

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junnit
Observer
Observer
667 Views
Registered: ‎05-10-2018

have you got some example codes now?I am facing the same question,I want to change the line rate trough DRP too in my Kintex7 device,thanks a lot.

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