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Observer
Observer
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Registered: ‎05-11-2018

Kintex 7 GTX Wizard ports missing

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Hi all,

 

Some Info:

---------------------

FPGA : Kintex 7 xc7k70tfbg676-1

Dev Suite : Vivado 2018.2

GT Type : GTX

GTX Wizard Version : 3.6

 

TX & RX Setting:

Linerate :: 2.56Gbps

width      :: 16 bits

ref clk     :: 160MHz

buffers both :: enabled

 

 

I am trying to get the recovered clock from the RX of the SFP in the  Kintex 7. In the manual (ug476_7Series_Transceivers.pdf pg 212), it says to set RXOUTCLKSEL = 3'b010 (Which is RXOUTCLKPM Path) and connect the RXOUTCLK for the recovered clock. Unfortunately, there is no port in the gtwizard_0.v wrapper with the given name! I have tried different settings, but could not get the  RXOUTCLKSEL to be visible.

 

I got the RXOUTCLK by setting it to "Include shared logic in example design" and RXUSRCLK Source,  but once I did that the wrapper changed, with the main difference being gt0_gtrefclk1_in which I used IBUFDS_GTE2 to convert the REF_IN differential pair. It did not give any error but the clock was not the recovered clock...

 

 

Help, I am new to this and have no idea how to solve it and looking at other answers didn't help...

 

 

Here is the connections for the gtwrapper...  

 

//==============================================================
// Create the SFP block.
//==============================================================

//Enable the sfp by setting the disable pin to zero
assign sfp_tx_disable_0 = zero; // enabling the sfps
assign sfp_tx_disable_1 = zero; // enabling the sfps

//setting the tx data value to be FF00 for hte
wire [15:0] data_value;
assign data_value = 16'hFF00;

//creating a new reset for GTX
reg reset_gtx;
always @(posedge clk40) reset_gtx <= reset_por;




//Reference Clock...
wire REFCLK_IN0,ref_clk0_in;


IBUFDS_GTE2 IBUFDS_REF_CLK
(
.I (refclk_p0), //ref clock p coming from outside
.IB (refclk_n0), //ref clock p coming from outside
.O (REFCLK_IN0) // ref clock that is sent to GT Wrapper...
);





// Recovered CLK out
wire RXOUTCLK1,RXOUTCLK0; //
wire RXOUTCLK_TX2;
BUFG BUFG_RXOUTCLK(.I(RXOUTCLK0),.O(RXOUTCLK_TX2)); // without the buffer it won't work for some reason...
assign tx2 = RXOUTCLK_TX2; //TX2 is connected to SMA cables...


//GTX Wizard wrapper...
gtwizard_0 GTX(
.soft_reset_tx_in(reset_gtx),
.soft_reset_rx_in(reset_gtx),
.dont_reset_on_data_error_in(one),

//Reference Clock in CLK1...
// .q0_clk1_gtrefclk_pad_n_in(refclk_n0),
// .q0_clk1_gtrefclk_pad_p_in(refclk_p0),

.gt0_gtrefclk1_in(REFCLK_IN0),
// .gt0_gtrefclk0_in(REFCLK_IN0),
.gt1_gtrefclk1_in(REFCLK_IN0),
// .gt1_gtrefclk0_in(REFCLK_IN0),


// .gt0_tx_fsm_reset_done_out(gt0_tx_fsm_reset_done_out),
// .gt0_rx_fsm_reset_done_out(gt0_rx_fsm_reset_done_out),
.gt0_data_valid_in(one),
// .gt1_tx_fsm_reset_done_out(gt1_tx_fsm_reset_done_out),
// .gt1_rx_fsm_reset_done_out(gt1_rx_fsm_reset_done_out),
.gt1_data_valid_in(one),

// .gt0_txusrclk_out(gt0_txusrclk_out),
// .gt0_txusrclk2_out(gt0_txusrclk2_out),
// .gt0_rxusrclk_out(gt0_rxusrclk_out),
// .gt0_rxusrclk2_out(gt0_rxusrclk2_out),

// .gt1_txusrclk_out(gt1_txusrclk_out),
// .gt1_txusrclk2_out(gt1_txusrclk2_out),
// .gt1_rxusrclk_out(gt1_rxusrclk_out),
// .gt1_rxusrclk2_out(gt1_rxusrclk2_out),
//_________________________________________________________________________
//GT0 (X1Y0)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
// .gt0_cpllfbclklost_out (gt0_cpllfbclklost_out), // output wire gt0_cpllfbclklost_out
// .gt0_cplllock_out (gt0_cplllock_out), // output wire gt0_cplllock_out
.gt0_cpllreset_in (reset_gtx), // input wire gt0_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt0_drpaddr_in (9'h0), // input wire [8:0] gt0_drpaddr_in
.gt0_drpdi_in (16'h0), // input wire [15:0] gt0_drpdi_in
// .gt0_drpdo_out (gt0_drpdo_out), // output wire [15:0] gt0_drpdo_out
.gt0_drpen_in (zero), // input wire gt0_drpen_in
// .gt0_drprdy_out (gt0_drprdy_out), // output wire gt0_drprdy_out
.gt0_drpwe_in (zero), // input wire gt0_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
// .gt0_dmonitorout_out (gt0_dmonitorout_out), // output wire [7:0] gt0_dmonitorout_out
//------------------- RX Initialization and Reset Ports --------------------
.gt0_eyescanreset_in (reset_gtx), // input wire gt0_eyescanreset_in
.gt0_rxuserrdy_in (one), // input wire gt0_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
// .gt0_eyescandataerror_out (gt0_eyescandataerror_out), // output wire gt0_eyescandataerror_out
.gt0_eyescantrigger_in (zero), // input wire gt0_eyescantrigger_in


//---------------- Receive Ports - FPGA RX interface Ports -----------------
// .gt0_rxdata_out (gt0_rxdata_out), // output wire [15:0] gt0_rxdata_out


//------------------------- Receive Ports - RX AFE -------------------------
.gt0_gtxrxp_in (sfp_rx_p0), // input wire gt0_gtxrxp_in
.gt0_gtxrxn_in (sfp_rx_n0), // input wire gt0_gtxrxn_in

//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt0_rxdfelpmreset_in (reset_gtx), // input wire gt0_rxdfelpmreset_in
// .gt0_rxmonitorout_out (gt0_rxmonitorout_out), // output wire [6:0] gt0_rxmonitorout_out
.gt0_rxmonitorsel_in (2'h1), // input wire [1:0] gt0_rxmonitorsel_in


//------------- Receive Ports - RX Fabric Output Control Ports -------------
.gt0_rxoutclk_out (RXOUTCLK0),
// .gt0_rxoutclkfabric_out (RXOUTCLK0), // output wire gt0_rxoutclkfabric_out



//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt0_gtrxreset_in (reset_gtx), // input wire gt0_gtrxreset_in
.gt0_rxpmareset_in (reset_gtx), // input wire gt0_rxpmareset_in
//------------ Receive Ports -RX Initialization and Reset Ports ------------
// .gt0_rxresetdone_out (gt0_rxresetdone_out), // output wire gt0_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt0_gttxreset_in (reset_gtx), // input wire gt0_gttxreset_in
.gt0_txuserrdy_in (one), // input wire gt0_txuserrdy_in
//---------------- Transmit Ports - TX Data Path interface -----------------
.gt0_txdata_in (data_value), // input wire [15:0] gt0_txdata_in
//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt0_gtxtxn_out (sfp_tx_n0), // output wire gt0_gtxtxn_out
.gt0_gtxtxp_out (sfp_tx_p0), // output wire gt0_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
// .gt0_txoutclkfabric_out (gt0_txoutclkfabric_out), // output wire gt0_txoutclkfabric_out
// .gt0_txoutclkpcs_out (gt0_txoutclkpcs_out), // output wire gt0_txoutclkpcs_out
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
// .gt0_txresetdone_out (gt0_txresetdone_out), // output wire gt0_txresetdone_out

//GT1 (X1Y3)
//____________________________CHANNEL PORTS________________________________
//------------------------------- CPLL Ports -------------------------------
// .gt1_cpllfbclklost_out (gt1_cpllfbclklost_out), // output wire gt1_cpllfbclklost_out
// .gt1_cplllock_out (gt1_cplllock_out), // output wire gt1_cplllock_out
.gt1_cpllreset_in (reset_gtx), // input wire gt1_cpllreset_in
//-------------------------- Channel - DRP Ports --------------------------
.gt1_drpaddr_in (9'h0), // input wire [8:0] gt1_drpaddr_in
.gt1_drpdi_in (16'h0), // input wire [15:0] gt1_drpdi_in
// .gt1_drpdo_out (gt1_drpdo_out), // output wire [15:0] gt1_drpdo_out
.gt1_drpen_in (zero), // input wire gt1_drpen_in
// .gt1_drprdy_out (gt1_drprdy_out), // output wire gt1_drprdy_out
.gt1_drpwe_in (zero), // input wire gt1_drpwe_in
//------------------------- Digital Monitor Ports --------------------------
// .gt1_dmonitorout_out (gt1_dmonitorout_out), // output wire [7:0] gt1_dmonitorout_out
//------------------- RX Initialization and Reset Ports --------------------
.gt1_eyescanreset_in (reset_gtx), // input wire gt1_eyescanreset_in
.gt1_rxuserrdy_in (one), // input wire gt1_rxuserrdy_in
//------------------------ RX Margin Analysis Ports ------------------------
// .gt1_eyescandataerror_out (gt1_eyescandataerror_out), // output wire gt1_eyescandataerror_out
.gt1_eyescantrigger_in (zero), // input wire gt1_eyescantrigger_in


//---------------- Receive Ports - FPGA RX interface Ports -----------------
// .gt1_rxdata_out (gt1_rxdata_out), // output wire [15:0] gt1_rxdata_out




//------------------------- Receive Ports - RX AFE -------------------------
.gt1_gtxrxp_in (sfp_rx_p1), // input wire gt1_gtxrxp_in
.gt1_gtxrxn_in (sfp_rx_n1), // input wire gt1_gtxrxn_in



//------------------- Receive Ports - RX Equalizer Ports -------------------
.gt1_rxdfelpmreset_in (reset_gtx), // input wire gt1_rxdfelpmreset_in
// .gt1_rxmonitorout_out (gt1_rxmonitorout_out), // output wire [6:0] gt1_rxmonitorout_out
.gt1_rxmonitorsel_in (2'h1), // input wire [1:0] gt1_rxmonitorsel_in


//------------- Receive Ports - RX Fabric Output Control Ports -------------
// .gt1_rxoutclkfabric_out (gt1_rxoutclkfabric_out), // output wire gt1_rxoutclkfabric_out
.gt1_rxoutclk_out (RXOUTCLK1),

//----------- Receive Ports - RX Initialization and Reset Ports ------------
.gt1_gtrxreset_in (reset_gtx), // input wire gt1_gtrxreset_in
.gt1_rxpmareset_in (reset_gtx), // input wire gt1_rxpmareset_in
//------------ Receive Ports -RX Initialization and Reset Ports ------------
// .gt1_rxresetdone_out (gt1_rxresetdone_out), // output wire gt1_rxresetdone_out
//------------------- TX Initialization and Reset Ports --------------------
.gt1_gttxreset_in (reset_gtx), // input wire gt1_gttxreset_in
.gt1_txuserrdy_in (one), // input wire gt1_txuserrdy_in



//---------------- Transmit Ports - TX Data Path interface -----------------
.gt1_txdata_in (data_value), // input wire [15:0] gt1_txdata_in



//-------------- Transmit Ports - TX Driver and OOB signaling --------------
.gt1_gtxtxn_out (sfp_tx_n1), // output wire gt1_gtxtxn_out
.gt1_gtxtxp_out (sfp_tx_p1), // output wire gt1_gtxtxp_out
//--------- Transmit Ports - TX Fabric Clock Output Control Ports ----------
// .gt1_txoutclkfabric_out (gt1_txoutclkfabric_out), // output wire gt1_txoutclkfabric_out
// .gt1_txoutclkpcs_out (gt1_txoutclkpcs_out), // output wire gt1_txoutclkpcs_out
//----------- Transmit Ports - TX Initialization and Reset Ports -----------
// .gt1_txresetdone_out (gt1_txresetdone_out), // output wire gt1_txresetdone_out

//____________________________COMMON PORTS________________________________
// .gt0_qplloutclk_out(gt0_qplloutclk_out),
// .gt0_qplloutrefclk_out(gt0_qplloutrefclk_out),
.sysclk_in(clk40) //What is this used for?

);

 

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Moderator
Moderator
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Registered: ‎07-30-2007

No, I'm afraid not.  The method I've described is the only way to get it done without making the core "unmanaged".  When you unmanage the core you would be able to edit all the files.   You would then have to dig into the design and route the rxoutclksel pins to the top of the design and from there you could change them as needed.  This is kind of tedious and you would lose any future updates to the core in new Vivado releases so it is not recommended.  




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Moderator
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Registered: ‎07-30-2007

 

If you choose the RXOUTCLK as the RXUSRCLK source and leave the RXPLLREFCLK unchecked as shown below.  It should set the RXOUTCLKSEL to what you are looking for.  See the 2nd image below.

 

RXOUTCLK.JPG

 

rxoutclksel.JPG

 

 

 

 




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Observer
Observer
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Registered: ‎05-11-2018

Hi, so if I want to change that port what should I do? and do I need to be in Include shared logic in example design option?

 

thanks a lot!!! :) 

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Moderator
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Registered: ‎07-30-2007

If you are trying to get the port set to 010 and don't need to change it dynamically you can just set the RXUSRCLK source to RXOUTCLK in the clocking and encoding tab in the GT wizard.  This is the normal use case.  Changing this port dynamically will be quite a bit more difficult in the 7-series wizard.  Will the static setting be enough?




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Observer
Observer
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Registered: ‎05-11-2018
Thanks, static should work for me. But is there any way to have the RXOUTCLK in the "Include Shared Logic in core" ?
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Registered: ‎07-30-2007

No, I'm afraid not.  The method I've described is the only way to get it done without making the core "unmanaged".  When you unmanage the core you would be able to edit all the files.   You would then have to dig into the design and route the rxoutclksel pins to the top of the design and from there you could change them as needed.  This is kind of tedious and you would lose any future updates to the core in new Vivado releases so it is not recommended.  




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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @rohithsaradhy,

 

I think Roy is referring to the RXOUTCLKSEL port of the GTX.

RXOUTCLK itself you do have as an output of the core in this case. It should be named like 'gt0_rxusrclk_out.

It is already buffered with a BUFG.

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Erik is right,  I was talking about the rxoutclksel.  The RXOUTCLK drives the RXUSRCLKs in the set up I showed above.




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Observer
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Hi,

Which schematic is this (The second  picture given by Roym) and how do I access this? I cannot find this particular port in schematic under rtl, synthesized, or implemented design.

 

thanks.

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What I do is:

1. synthesize the design

2. open the synthesized design

3. zoom in on the transceiver and Select a single transceiver pin

4 right click on the transceiver pin and in that menu you will click on  "schematic"

 

When you open the schematic in that manner it should show just the single transceiver.  From there you could double click on any pin to trace it and the *sel pins will show up as shown above.




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