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Contributor
Contributor
1,022 Views
Registered: ‎04-18-2015

LVPECL oscillator

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Hi all,

Iam using a lvpecl oscillator for my MGT refclocks. (156.25).the termination to be provided is AC termination for MGT's.

i have followed as follows 150 0hms near oscillator and capacitor.

 

 

lvpecl.jpg

 

but is it required to add 50 ohms pull down resistors near reciever?or FPGA internal termination can be  enabled for LVPECL t  catering to 50 ohms functionality near fpga??

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Xilinx Employee
Xilinx Employee
1,280 Views
Registered: ‎11-29-2007

Re: LVPECL oscillator

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hello,

for short, ideal, low loss channels as in the REFCLK case, the LVDS signal measured at input pins is electrically compatible. I would recommend LVDS especially for UltraScale and UltraScale+ devices where the bidirectional buffer is sensitive to too wide signal swing.

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4 Replies
Scholar jmcclusk
Scholar
1,004 Views
Registered: ‎02-24-2014

Re: LVPECL oscillator

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In all the FPGA families, the MGT refclock inputs have 50 ohm internal termination.   Don't attach any external termination resistors.   All they need is the AC coupling capacitor.

Don't forget to close a thread when possible by accepting a post as a solution.
Contributor
Contributor
976 Views
Registered: ‎04-18-2015

Re: LVPECL oscillator

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Oscillator we selected is CDCM61004 from TI. which can give outputs LVDS/LVPECL,for MGT's is it better to select LVPECL?since LVPECL is having more swing compared to LVDS.is internal terminations internaly selected according to IOSTANDARD?

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Scholar jmcclusk
Scholar
959 Views
Registered: ‎02-24-2014

Re: LVPECL oscillator

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Either LVDS or LVPECL will work, but I tend to favor LVDS drivers, since they don't need external resistors.

Don't forget to close a thread when possible by accepting a post as a solution.
Xilinx Employee
Xilinx Employee
1,281 Views
Registered: ‎11-29-2007

Re: LVPECL oscillator

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hello,

for short, ideal, low loss channels as in the REFCLK case, the LVDS signal measured at input pins is electrically compatible. I would recommend LVDS especially for UltraScale and UltraScale+ devices where the bidirectional buffer is sensitive to too wide signal swing.

View solution in original post