UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Explorer
Explorer
666 Views
Registered: ‎10-12-2018

Linerate confusion using 7series (VC707) IBERT

Jump to solution

I want to scan the eye-diagram of my high speed link.

I tried to use IBERT example design on VC707 board. I have set linerate to 5Gbps

image.png

BUT when I test the design near-end-PMA-loopback mode (on my VC707 board) the link state shows 10Gbps:

image.png

Why?

I use:

  • Win 10
  • Vivado 2017.4
  • VC707 (xc7vx485tffg1761-2)
  • IBERT

 

 

0 Kudos
1 Solution

Accepted Solutions
Explorer
Explorer
585 Views
Registered: ‎10-12-2018

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

I found the problem/solution.

Brief:

Do not modify the line-rate of an IBERT, If you need the change, generate a new example design too.

Reason:

The line-rate cannot be changed of an IBERT, because the constraint file wont updated for the new values. (I dont know if is it a bug or a feature.) So if you dont want to modify the PLL and clock constrains by hand in the *.xdc file open a new example design.

View solution in original post

0 Kudos
5 Replies
Xilinx Employee
Xilinx Employee
655 Views
Registered: ‎10-19-2011

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

Hi @betontalpfa ,

what is your system clock setup and what do you use actually on the board?

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
0 Kudos
Explorer
Explorer
646 Views
Registered: ‎10-12-2018

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

I have regenerated the project from scratch. And now its working well.

Maybe you, @eschidl, have found the solution.

Here is the Clock Settings of the WRONG desing (These are the default settings)

image.png

 

Here is the Clock Settings of the GOOD design (I switched to use QUAD clock)

image.png

Does this system clock measure the actual line rate?

0 Kudos
Xilinx Employee
Xilinx Employee
638 Views
Registered: ‎10-19-2011

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

Hi @betontalpfa ,

yes, the system clock is used for the measurement.

Good to hear that it is working with the refclk as system clock for you.

I would actually expect both setups to work.
The only thing to try with the SYSCLK pins as system clock would be to divide it down.
The 200MHz system clock is above the DRP limit. So a division is necessary internally.
If that is the problem, you could try to setup the IBERT core with the same pin locations but a frequency of 100MHz. Then in the example design toplevel put a clock divider by 2 between the sysclk pins and the clock input of the IBERT core.

------------------------------------------------------------------------------
Don't forget to reply, give kudo and accept as solution
------------------------------------------------------------------------------
Explorer
Explorer
610 Views
Registered: ‎10-12-2018

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

Hi @eschidl 

I have confused again.

I have set the linerate to 1Gbps (Now I using CPLL because of the slow linerate.)

image.png

Now I dont use external system clock. I use the GTREFCLK (of the same quad) as system clock, which is a 125MHz clock.

image.png

However, the result is confusing again. I have set (PMA or PCS) near-end loopback, and it shows 2.5Gbps:

image.png

I have attached the properties of the common block and the channel.

Why is this mismatch occure?

Can I trust in the MGTREFCLK's 125MHz?

0 Kudos
Explorer
Explorer
586 Views
Registered: ‎10-12-2018

Re: Linerate confusion using 7series (VC707) IBERT

Jump to solution

I found the problem/solution.

Brief:

Do not modify the line-rate of an IBERT, If you need the change, generate a new example design too.

Reason:

The line-rate cannot be changed of an IBERT, because the constraint file wont updated for the new values. (I dont know if is it a bug or a feature.) So if you dont want to modify the PLL and clock constrains by hand in the *.xdc file open a new example design.

View solution in original post

0 Kudos