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Scholar
Scholar
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Registered: ‎12-07-2018

Low-Jitter clocks for Aurora 64B/66B

Hello, I'm looking at PG074 documenation for the Aurora 64B/66B IP page 64 and 65. Page 64 Shows an Init_clk and a gt_refclk. Correct me if I'm wrong but these are two external clock inputs. On page 65 it says to use low-jitter clocks. How much jitter is allowed? I am generating a 156.25Mhz clock that has a about 79.9 RMS Jitter (fs). Is that okay?

 

Thank you,

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Joe @joe306 

>Correct me if I'm wrong but these are two external clock inputs.
>On page 65 it says to use low-jitter clocks. How much jitter is allowed?

Yes, your understanding is correct.
1. We do recommended free-run init_clk to be stable and feed from external input.
   (init_clk can be feed from internal clock generator, if you can ensure clock signal is free-run and stable before you start Aurora 64B66B IP initialization)
2. ref_clk definitely needs a clean external source with a good phase noise performance.

>I am generating a 156.25Mhz clock that has a about 79.9 RMS Jitter (fs). Is that okay?

Transceivers is very sensitive to a certain frequency noise, hence ref_clk needs a clock signal with a good phase noise performance.
The phase noise requirement for each device is described in the device datasheet.

For example if you are using UltraScale+ Kintex , please check DS922.
would you be able to check ref_clk phase noise on your clock source ?

KUS+_PHASE_NOISE.png
Thank you,
Leo

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Scholar
Scholar
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Registered: ‎12-07-2018

Hello, thank you for responding to my message. I am using a Zynq Ultrascale+ MPSoC FPGA.

 

Joe

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-30-2016

Hello Joe @joe306 

You need to check DS925 for your device.
But, the phase noise spec number is pretty similar with above table.


Thanks
Leo