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Visitor
Visitor
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Registered: ‎11-12-2020

MGT Clock

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Hello everyone,

Currently I am researching the SFP module on ARTIX 7 board but the problem is as follows:

 The first, I used the GIG_Ethernet PCS / PMA core in the IP Catalog to SGMII mode to loopback 1 SFP module successfully. However, I need to use 2 GIG_Ethernet PCS / PMA cores for 2 SFP ports, there is only 1 pair of pins MGT_CLK so it is not enough because each GIG_Ethernet PCS / PMA core requires 1 pair of MGT_CLK pins (I use board ALIX ARTIX 7). I want to ask is there a way to divide MGT_CLK into multiple CLK used for SFP ports? (I tried assigning signal but failed). Does the IP catalog support any core that allows dividing MGT_CLK?
The second problem I want to ask is when I use the ARTIX 7 board running 2 GIG_Ethernet PCS / PMA cores in the IP Catalog with the error "[Place 30-640] Place Check: This design requires more GTPE2_COMMON cells than are available in the target. This design requires 2 of such cell types but only 1 compatible site is available in the target device.Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.If so, please consider targeting a larger device . " Hope you support!
Thanks!!!

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Xilinx Employee
Xilinx Employee
530 Views
Registered: ‎10-19-2011

Hi @Dat,

I think you missed the share of the COMMON and the refclk buffer. There are still two of them in the design. You should reduce it to just one of them.
You implemented the example designs of the two cores fully.
In the design with the core with selection of shared logic in example design you need to remove the COMMON block instantiation as well as the IBUFDS_GTE instantiation and connect them with the signals of the other core.

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Visitor
Visitor
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Registered: ‎11-12-2020
I hope the answer from you!!! Thank you!!!
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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @Dat,

please have a look at UG482. It shows you how the transceivers are available in Artix-7. Figure 1-2 on page 14 gives you an overview of a quad. Your device only has one quad it seems. You see from the picture that in order to use the CHANNELs independently they have to work with the single COMMON block.

You probably created your IP cores with the option to put the shared logic into the core. With this you instantiate two COMMON blocks, which is obviously not possible. You will need to select during the core generation to put the shared logic into the example design. This will move the COMMON instantiation, and also the refclk input buffer, outside of the core. You will still need them, so you have to place them yourself then into your design. But here you can use them for both cores in parallel. If you use the same PLL for both core you will need to separate the PLL reset from the cores, as you would otherwise have a dependency of the cores. You could also move one core to the other PLL if needed.

An easy way for this should be to create one IP core with the 'Shared Logic within the core' and the other with 'Shared logic in example design'. The IP should provide port signals to connect the cores to share the COMMON block. Maybe you could give this also a try.

 

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Visitor
Visitor
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Registered: ‎11-12-2020

HI @eschidl , 

Thank you very much about your solution proposed. I've tried to create one IP core with the 'Shared Logic within the core' and the other with 'Shared logic in example design' but not success. Because I want to use two QUAD SFP for 2 IP core without using two refclk_SFP. Can you help me? I attach some documents of board Artix-7 I'm using (xc7a100tfgg484-2).

Thank you so much!!!

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎10-19-2011

Hi @Dat,

when you select 'Include Shared Logic in Core' the core will include the refclk input buffer and the COMMON block. You can see that the gtrefclk_in input is differential.
The core provides the outputs of the refclk input buffer with gtrefclk_out and gtrefclk_bufg_out.
The core with 'Include Shared Logic in Example Design' has the inputs gtrefclk and gtrefclk_bufg. Connect these directly to the outputs of the other core. With this you can use just one refclk input for both IP.

Similarly the first core provides access of the PLL outputs to be used with the second core if you want to share the PLL..

You could also use both cores with the setting 'Include Shared Logic in Example Design' and instantiate the input buffer and COMMON block yourself like it is done in the example design then. Here you could control how the PLL is reset independently of the cores to have the cores independent of each other.

In you schematics you have a termination resistor R22 on the refclk input. This is not necessary. The input is terminated internally. Please remove that resistor (and the stubs in the layout).

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Visitor
Visitor
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Registered: ‎11-12-2020

Hi @eschidl , Thank you very much about your help. I selected core 'Include Shared Logic in Core'  and other core 'Include Shared Logic in Example Design'. then, I connected two core but using one gtrefclk. However, the error "[Place 30-640] Place Check: This design requires more GTPE2_COMMON cells than are available in the target. This design requires 2 of such cell types but only 1 compatible site is available in the target device.Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected.If so, please consider targeting a larger device ." still existed. Can you help me fix the error? I can access https://www.dropbox.com/s/aisuxt3vbe4kf8n/Thu_nghiem_clock.rar?dl=0  to reference the project which I was doing before. (because the maximum file size in forum is 19 MB so I can't attach in here).

Thank you!

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Xilinx Employee
Xilinx Employee
531 Views
Registered: ‎10-19-2011

Hi @Dat,

I think you missed the share of the COMMON and the refclk buffer. There are still two of them in the design. You should reduce it to just one of them.
You implemented the example designs of the two cores fully.
In the design with the core with selection of shared logic in example design you need to remove the COMMON block instantiation as well as the IBUFDS_GTE instantiation and connect them with the signals of the other core.

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Visitor
Visitor
513 Views
Registered: ‎11-12-2020

Hi @eschidl ,

I want to send you my most sincere gratitude. I have tried the method you purposed and succeeded for the project. Thanks to the forum for being able to connect with the FPGA community as well as the technical employees of Xillinx!!!

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