cancel
Showing results for
Show  only  | Search instead for
Did you mean:
Observer
1,429 Views
Registered: ‎09-21-2018

## MGT Reference Clock Input Common Mode Voltage

We are designing a board that uses the GTY transceivers in a Zynq US+ MPSoC.  Am I correct that the MGT reference clock common mode input voltage would be VMGTAVCC = 0.9V for the Zynq, based on the internal biasing shown in UG578 Figure 2-1?

Assuming the input common mode voltage is 0.9V and we use AC-coupling, then the clock input differential voltage would have to stay below 800mVpp to comply with the max VMGTREFCLK spec of 1.3V in DS925 Table 1 (i.e. 0.9V + 800mVpp/2 = 1.3V)?  This 800mVpp max differential input voltage is much lower than the 2000mVpp spec given in DS925 Table 109 for VIDIFF?  What am i missing?  How would it ever be possible to achieve the VIDIFF = 2000mVpp given in Table 109 without running up against the absolute 1.3V VMGTREFCLK limit of Table 1?  Is it possible to change the internal MGTREFCLK bias, or disable it and use external DC bias?

Thanks, Ted

1 Solution

Accepted Solutions
Mentor
1,391 Views
Registered: ‎01-08-2012

VIDIFF = 2000mVpp is a differential measurement, i.e. the voltage measured between the two lines.  The voltage on each wire only needs to change +/- 500mV to give a 2000mVp-p differential measurement.

+/-500mV around a Vcm of 0.9V means the voltage on each pin goes between 400mV and 1400mV, which is still outside the DS925 limits of -0.5 to +1.3V.

Solutions would involve either reducing VIDIFF to less than 1.6Vp-p, or reducing VCM to 0.8V or less (around 0.4V to 0.5V would be best).

I can see ways of adjusting the common mode voltage for transceiver data inputs, but not for the MGTREFCLK inputs.  This means the only practical solution for you (or indeed anyone using these devices with AC coupled clocks) is to ensure that VIDIFF is less than 1.6Vp-p.

3 Replies
Mentor
1,392 Views
Registered: ‎01-08-2012

VIDIFF = 2000mVpp is a differential measurement, i.e. the voltage measured between the two lines.  The voltage on each wire only needs to change +/- 500mV to give a 2000mVp-p differential measurement.

+/-500mV around a Vcm of 0.9V means the voltage on each pin goes between 400mV and 1400mV, which is still outside the DS925 limits of -0.5 to +1.3V.

Solutions would involve either reducing VIDIFF to less than 1.6Vp-p, or reducing VCM to 0.8V or less (around 0.4V to 0.5V would be best).

I can see ways of adjusting the common mode voltage for transceiver data inputs, but not for the MGTREFCLK inputs.  This means the only practical solution for you (or indeed anyone using these devices with AC coupled clocks) is to ensure that VIDIFF is less than 1.6Vp-p.

Observer
1,362 Views
Registered: ‎09-21-2018

Thanks Allan

Visitor
167 Views
Registered: ‎05-27-2015

I have a similar question regarding the MGTREFCLK inputs, we are trying to connect HCSL logic clock as input into the MGTREFCLK pins of a GT bank in Kintex US+ device, we even simulated this scenario (but not with MGTREFCLK IBIS, we used HP_LVDS_DT_AC_COUPLED_I model instead).

I am attaching the screenshots of the results of simulation, can you please have a look at it and let me know if you see any mismatch in the levels? or anything i need to change in the design of my PCB?

Thank you!!