We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Showing results for 
Search instead for 
Did you mean: 
Observer akshay_acharya
Registered: ‎10-11-2018

MGT refclk given to IBERT

Hello sir/madam,

1. In IBERT if the line rate is 12gbps and the DATA_WIDTH = 40. then how much should be MGT_refclk frequency?
Accoring to my knowledge, line rate = DATA_WIDTH * MGT_refclk. Is it proper ? or can I provide any other Frequency? and how to control the value of N in the QPLL?

2. The link is not setting for 12gbps, but it is working fine for 6gbps. What are the changes need to be done in the RX_CDR?

3. I have taken care of the CTLE and DFE configuration, Sometimes the link is set and it is not stable.

How to attain a proper link between the 2 boards, with high line rates?

4. In IBERT core, RXOUTCLK is there is it recovered clock from the RX_CDR?



Akshay kumar

0 Kudos
1 Reply
Xilinx Employee
Xilinx Employee
Registered: ‎08-07-2007

回复: MGT refclk given to IBERT

hi @akshay_acharya 


in IBERT customizing GUI, you can select line rate and data width first.

Then if you click on the refclk, it will show you a drop-down list for all the valid reference clocks.

it can be linerate/40 but it is not limited to this frequency.

You can pick up any one and make sure you can provide the same on the board.

IBERT will take care of the QPLL settings. 


if 6Gbps is ok but 12G is unstable, you can try LPM mode.

You can also try changing the remote partner TX amplitude, and emphasis.




Don't forget to reply, give kudo and accept as solution
0 Kudos